1 // Copyright 2015 The Go Authors. All rights reserved.
2 // Use of this source code is governed by a BSD-style
3 // license that can be found in the LICENSE file.
4
5 // Lowering arithmetic
6 (Add(64|32|16|8) ...) => (ADD(Q|L|L|L) ...)
7 (AddPtr ...) => (ADDQ ...)
8 (Add(32|64)F ...) => (ADDS(S|D) ...)
9
10 (Sub(64|32|16|8) ...) => (SUB(Q|L|L|L) ...)
11 (SubPtr ...) => (SUBQ ...)
12 (Sub(32|64)F ...) => (SUBS(S|D) ...)
13
14 (Mul(64|32|16|8) ...) => (MUL(Q|L|L|L) ...)
15 (Mul(32|64)F ...) => (MULS(S|D) ...)
16
17 (Select0 (Mul64uover x y)) => (Select0 <typ.UInt64> (MULQU x y))
18 (Select0 (Mul32uover x y)) => (Select0 <typ.UInt32> (MULLU x y))
19 (Select1 (Mul(64|32)uover x y)) => (SETO (Select1 <types.TypeFlags> (MUL(Q|L)U x y)))
20
21 (Hmul(64|32) ...) => (HMUL(Q|L) ...)
22 (Hmul(64|32)u ...) => (HMUL(Q|L)U ...)
23
24 (Div(64|32|16) [a] x y) => (Select0 (DIV(Q|L|W) [a] x y))
25 (Div8 x y) => (Select0 (DIVW (SignExt8to16 x) (SignExt8to16 y)))
26 (Div(64|32|16)u x y) => (Select0 (DIV(Q|L|W)U x y))
27 (Div8u x y) => (Select0 (DIVWU (ZeroExt8to16 x) (ZeroExt8to16 y)))
28 (Div(32|64)F ...) => (DIVS(S|D) ...)
29
30 (Select0 (Add64carry x y c)) => (Select0 (ADCQ x y (Select1 <types.TypeFlags> (NEGLflags c))))
31 (Select1 (Add64carry x y c)) => (MOVBQZX (SETB <types.Types[types.TUINT8]> (Select1 <types.TypeFlags> (ADCQ x y (Select1 <types.TypeFlags> (NEGLflags c))))))
32 (Select0 (Sub64borrow x y c)) => (Select0 (SBBQ x y (Select1 <types.TypeFlags> (NEGLflags c))))
33 (Select1 (Sub64borrow x y c)) => (MOVBQZX (SETB <types.Types[types.TUINT8]> (Select1 <types.TypeFlags> (SBBQ x y (Select1 <types.TypeFlags> (NEGLflags c))))))
34 // Optimize ADCQ and friends
35 (ADCQ x (MOVQconst [c]) carry) && is32Bit(c) => (ADCQconst x [int32(c)] carry)
36 (ADCQ x y (FlagEQ)) => (ADDQcarry x y)
37 (ADCQconst x [c] (FlagEQ)) => (ADDQconstcarry x [c])
38 (ADDQcarry x (MOVQconst [c])) && is32Bit(c) => (ADDQconstcarry x [int32(c)])
39 (SBBQ x (MOVQconst [c]) borrow) && is32Bit(c) => (SBBQconst x [int32(c)] borrow)
40 (SBBQ x y (FlagEQ)) => (SUBQborrow x y)
41 (SBBQconst x [c] (FlagEQ)) => (SUBQconstborrow x [c])
42 (SUBQborrow x (MOVQconst [c])) && is32Bit(c) => (SUBQconstborrow x [int32(c)])
43 (Select1 (NEGLflags (MOVQconst [0]))) => (FlagEQ)
44 (Select1 (NEGLflags (MOVBQZX (SETB x)))) => x
45 // Absorb InvertFlags into ADCQ/SBBQ: CF(InvertFlags(f)) = SETA(f), so
46 // re-materialize the carry/borrow through the SETA+NEGLflags path.
47 (ADCQ x y (InvertFlags f)) => (ADCQ x y (Select1 <types.TypeFlags> (NEGLflags (MOVBQZX <types.Types[types.TUINT32]> (SETA <types.Types[types.TUINT8]> f)))))
48 (ADCQconst x [c] (InvertFlags f)) => (ADCQconst x [c] (Select1 <types.TypeFlags> (NEGLflags (MOVBQZX <types.Types[types.TUINT32]> (SETA <types.Types[types.TUINT8]> f)))))
49 (SBBQ x y (InvertFlags f)) => (SBBQ x y (Select1 <types.TypeFlags> (NEGLflags (MOVBQZX <types.Types[types.TUINT32]> (SETA <types.Types[types.TUINT8]> f)))))
50 (SBBQconst x [c] (InvertFlags f)) => (SBBQconst x [c] (Select1 <types.TypeFlags> (NEGLflags (MOVBQZX <types.Types[types.TUINT32]> (SETA <types.Types[types.TUINT8]> f)))))
51
52
53 (Mul64uhilo ...) => (MULQU2 ...)
54 (Div128u ...) => (DIVQU2 ...)
55
56 (Avg64u ...) => (AVGQU ...)
57
58 (Mod(64|32|16) [a] x y) => (Select1 (DIV(Q|L|W) [a] x y))
59 (Mod8 x y) => (Select1 (DIVW (SignExt8to16 x) (SignExt8to16 y)))
60 (Mod(64|32|16)u x y) => (Select1 (DIV(Q|L|W)U x y))
61 (Mod8u x y) => (Select1 (DIVWU (ZeroExt8to16 x) (ZeroExt8to16 y)))
62
63 (And(64|32|16|8) ...) => (AND(Q|L|L|L) ...)
64 (Or(64|32|16|8) ...) => (OR(Q|L|L|L) ...)
65 (Xor(64|32|16|8) ...) => (XOR(Q|L|L|L) ...)
66 (Com(64|32|16|8) ...) => (NOT(Q|L|L|L) ...)
67
68 (Neg(64|32|16|8) ...) => (NEG(Q|L|L|L) ...)
69 (Neg32F x) => (PXOR x (MOVSSconst <typ.Float32> [float32(math.Copysign(0, -1))]))
70 (Neg64F x) => (PXOR x (MOVSDconst <typ.Float64> [math.Copysign(0, -1)]))
71
72 // Lowering boolean ops
73 (AndB ...) => (ANDL ...)
74 (OrB ...) => (ORL ...)
75 (Not x) => (XORLconst [1] x)
76
77 // Lowering pointer arithmetic
78 (OffPtr [off] ptr) && is32Bit(off) => (ADDQconst [int32(off)] ptr)
79 (OffPtr [off] ptr) => (ADDQ (MOVQconst [off]) ptr)
80
81 // Lowering other arithmetic
82 (Ctz64 x) && buildcfg.GOAMD64 >= 3 => (TZCNTQ x)
83 (Ctz32 x) && buildcfg.GOAMD64 >= 3 => (TZCNTL x)
84 (Ctz64 <t> x) && buildcfg.GOAMD64 < 3 => (CMOVQEQ (Select0 <t> (BSFQ x)) (MOVQconst <t> [64]) (Select1 <types.TypeFlags> (BSFQ x)))
85 (Ctz32 x) && buildcfg.GOAMD64 < 3 => (Select0 (BSFQ (BTSQconst <typ.UInt64> [32] x)))
86 (Ctz16 x) => (BSFL (ORLconst <typ.UInt32> [1<<16] x))
87 (Ctz8 x) => (BSFL (ORLconst <typ.UInt32> [1<<8 ] x))
88
89 (Ctz64NonZero x) && buildcfg.GOAMD64 >= 3 => (TZCNTQ x)
90 (Ctz32NonZero x) && buildcfg.GOAMD64 >= 3 => (TZCNTL x)
91 (Ctz16NonZero x) && buildcfg.GOAMD64 >= 3 => (TZCNTL x)
92 (Ctz8NonZero x) && buildcfg.GOAMD64 >= 3 => (TZCNTL x)
93 (Ctz64NonZero x) && buildcfg.GOAMD64 < 3 => (Select0 (BSFQ x))
94 (Ctz32NonZero x) && buildcfg.GOAMD64 < 3 => (BSFL x)
95 (Ctz16NonZero x) && buildcfg.GOAMD64 < 3 => (BSFL x)
96 (Ctz8NonZero x) && buildcfg.GOAMD64 < 3 => (BSFL x)
97
98 // BitLen64 of a 64 bit value x requires checking whether x == 0, since BSRQ is undefined when x == 0.
99 // However, for zero-extended values, we can cheat a bit, and calculate
100 // BSR(x<<1 + 1), which is guaranteed to be non-zero, and which conveniently
101 // places the index of the highest set bit where we want it.
102 // For GOAMD64>=3, BitLen can be calculated by OperandSize - LZCNT(x).
103 (BitLen64 <t> x) && buildcfg.GOAMD64 < 3 => (ADDQconst [1] (CMOVQEQ <t> (Select0 <t> (BSRQ x)) (MOVQconst <t> [-1]) (Select1 <types.TypeFlags> (BSRQ x))))
104 (BitLen32 x) && buildcfg.GOAMD64 < 3 => (Select0 (BSRQ (LEAQ1 <typ.UInt64> [1] (MOVLQZX <typ.UInt64> x) (MOVLQZX <typ.UInt64> x))))
105 (BitLen16 x) && buildcfg.GOAMD64 < 3 => (BSRL (LEAL1 <typ.UInt32> [1] (MOVWQZX <typ.UInt32> x) (MOVWQZX <typ.UInt32> x)))
106 (BitLen8 x) && buildcfg.GOAMD64 < 3 => (BSRL (LEAL1 <typ.UInt32> [1] (MOVBQZX <typ.UInt32> x) (MOVBQZX <typ.UInt32> x)))
107 (BitLen64 <t> x) && buildcfg.GOAMD64 >= 3 => (NEGQ (ADDQconst <t> [-64] (LZCNTQ x)))
108 // Use 64-bit version to allow const-fold remove unnecessary arithmetic.
109 (BitLen32 <t> x) && buildcfg.GOAMD64 >= 3 => (NEGQ (ADDQconst <t> [-32] (LZCNTL x)))
110 (BitLen16 <t> x) && buildcfg.GOAMD64 >= 3 => (NEGQ (ADDQconst <t> [-32] (LZCNTL (MOVWQZX <x.Type> x))))
111 (BitLen8 <t> x) && buildcfg.GOAMD64 >= 3 => (NEGQ (ADDQconst <t> [-32] (LZCNTL (MOVBQZX <x.Type> x))))
112
113 (Bswap(64|32) ...) => (BSWAP(Q|L) ...)
114 (Bswap16 x) => (ROLWconst [8] x)
115
116 (PopCount(64|32) ...) => (POPCNT(Q|L) ...)
117 (PopCount16 x) => (POPCNTL (MOVWQZX <typ.UInt32> x))
118 (PopCount8 x) => (POPCNTL (MOVBQZX <typ.UInt32> x))
119
120 (Sqrt ...) => (SQRTSD ...)
121 (Sqrt32 ...) => (SQRTSS ...)
122
123 (RoundToEven x) => (ROUNDSD [0] x)
124 (Floor x) => (ROUNDSD [1] x)
125 (Ceil x) => (ROUNDSD [2] x)
126 (Trunc x) => (ROUNDSD [3] x)
127
128 (CVTSD2SS (ROUNDSD [c] (CVTSS2SD x))) => (ROUNDSS [c] x)
129
130 (FMA x y z) => (VFMADD231SD z x y)
131
132 // Lowering extension
133 // Note: we always extend to 64 bits even though some ops don't need that many result bits.
134 (SignExt8to16 ...) => (MOVBQSX ...)
135 (SignExt8to32 ...) => (MOVBQSX ...)
136 (SignExt8to64 ...) => (MOVBQSX ...)
137 (SignExt16to32 ...) => (MOVWQSX ...)
138 (SignExt16to64 ...) => (MOVWQSX ...)
139 (SignExt32to64 ...) => (MOVLQSX ...)
140
141 (ZeroExt8to16 ...) => (MOVBQZX ...)
142 (ZeroExt8to32 ...) => (MOVBQZX ...)
143 (ZeroExt8to64 ...) => (MOVBQZX ...)
144 (ZeroExt16to32 ...) => (MOVWQZX ...)
145 (ZeroExt16to64 ...) => (MOVWQZX ...)
146 (ZeroExt32to64 ...) => (MOVLQZX ...)
147
148 (Slicemask <t> x) => (SARQconst (NEGQ <t> x) [63])
149
150 (SpectreIndex <t> x y) => (CMOVQCC x (MOVQconst [0]) (CMPQ x y))
151 (SpectreSliceIndex <t> x y) => (CMOVQHI x (MOVQconst [0]) (CMPQ x y))
152
153 // Lowering truncation
154 // Because we ignore high parts of registers, truncates are just copies.
155 (Trunc16to8 ...) => (Copy ...)
156 (Trunc32to8 ...) => (Copy ...)
157 (Trunc32to16 ...) => (Copy ...)
158 (Trunc64to8 ...) => (Copy ...)
159 (Trunc64to16 ...) => (Copy ...)
160 (Trunc64to32 ...) => (Copy ...)
161
162 // Lowering float <-> int
163 (Cvt32to32F ...) => (CVTSL2SS ...)
164 (Cvt32to64F ...) => (CVTSL2SD ...)
165 (Cvt64to32F ...) => (CVTSQ2SS ...)
166 (Cvt64to64F ...) => (CVTSQ2SD ...)
167
168 // Float, to int.
169 // To make AMD64 "overflow" return max positive instead of max negative, compute
170 // y and not x, smear the sign bit, and xor.
171 (Cvt32Fto32 <t> x) && base.ConvertHash.MatchPos(v.Pos, nil) => (XORL <t> y (SARLconst <t> [31] (ANDL <t> y:(CVTTSS2SL <t> x) (NOTL <typ.Int32> (MOVLf2i x)))))
172 (Cvt64Fto32 <t> x) && base.ConvertHash.MatchPos(v.Pos, nil) => (XORL <t> y (SARLconst <t> [31] (ANDL <t> y:(CVTTSD2SL <t> x) (NOTL <typ.Int32> (MOVLf2i (CVTSD2SS <typ.Float32> x))))))
173
174 (Cvt32Fto64 <t> x) && base.ConvertHash.MatchPos(v.Pos, nil) => (XORQ <t> y (SARQconst <t> [63] (ANDQ <t> y:(CVTTSS2SQ <t> x) (NOTQ <typ.Int64> (MOVQf2i (CVTSS2SD <typ.Float64> x))) )))
175 (Cvt64Fto64 <t> x) && base.ConvertHash.MatchPos(v.Pos, nil) => (XORQ <t> y (SARQconst <t> [63] (ANDQ <t> y:(CVTTSD2SQ <t> x) (NOTQ <typ.Int64> (MOVQf2i x)))))
176
177 (Cvt32Fto32 <t> x) && !base.ConvertHash.MatchPos(v.Pos, nil) => (CVTTSS2SL <t> x)
178 (Cvt32Fto64 <t> x) && !base.ConvertHash.MatchPos(v.Pos, nil) => (CVTTSS2SQ <t> x)
179 (Cvt64Fto32 <t> x) && !base.ConvertHash.MatchPos(v.Pos, nil) => (CVTTSD2SL <t> x)
180 (Cvt64Fto64 <t> x) && !base.ConvertHash.MatchPos(v.Pos, nil) => (CVTTSD2SQ <t> x)
181
182 (Cvt32Fto64F ...) => (CVTSS2SD ...)
183 (Cvt64Fto32F ...) => (CVTSD2SS ...)
184
185 (Round(32|64)F ...) => (LoweredRound(32|64)F ...)
186
187 // Floating-point min is tricky, as the hardware op isn't right for various special
188 // cases (-0 and NaN). We use two hardware ops organized just right to make the
189 // result come out how we want it. See https://github.com/golang/go/issues/59488#issuecomment-1553493207
190 // (although that comment isn't exactly right, as the value overwritten is not simulated correctly).
191 // t1 = MINSD x, y => incorrect if x==NaN or x==-0,y==+0
192 // t2 = MINSD t1, x => fixes x==NaN case
193 // res = POR t1, t2 => fixes x==-0,y==+0 case
194 // Note that this trick depends on the special property that (NaN OR x) produces a NaN (although
195 // it might not produce the same NaN as the input).
196 (Min(64|32)F <t> x y) => (POR (MINS(D|S) <t> (MINS(D|S) <t> x y) x) (MINS(D|S) <t> x y))
197 // Floating-point max is even trickier. Punt to using min instead.
198 // max(x,y) == -min(-x,-y)
199 (Max(64|32)F <t> x y) => (Neg(64|32)F <t> (Min(64|32)F <t> (Neg(64|32)F <t> x) (Neg(64|32)F <t> y)))
200
201 (CvtBoolToUint8 ...) => (Copy ...)
202
203 // Lowering shifts
204 // Unsigned shifts need to return 0 if shift amount is >= width of shifted value.
205 // result = (arg << shift) & (shift >= argbits ? 0 : 0xffffffffffffffff)
206 (Lsh64x(64|32|16|8) <t> x y) && !shiftIsBounded(v) => (ANDQ (SHLQ <t> x y) (SBBQcarrymask <t> (CMP(Q|L|W|B)const y [64])))
207 (Lsh32x(64|32|16|8) <t> x y) && !shiftIsBounded(v) => (ANDL (SHLL <t> x y) (SBBLcarrymask <t> (CMP(Q|L|W|B)const y [32])))
208 (Lsh16x(64|32|16|8) <t> x y) && !shiftIsBounded(v) => (ANDL (SHLL <t> x y) (SBBLcarrymask <t> (CMP(Q|L|W|B)const y [32])))
209 (Lsh8x(64|32|16|8) <t> x y) && !shiftIsBounded(v) => (ANDL (SHLL <t> x y) (SBBLcarrymask <t> (CMP(Q|L|W|B)const y [32])))
210
211 (Lsh64x(64|32|16|8) x y) && shiftIsBounded(v) => (SHLQ x y)
212 (Lsh32x(64|32|16|8) x y) && shiftIsBounded(v) => (SHLL x y)
213 (Lsh16x(64|32|16|8) x y) && shiftIsBounded(v) => (SHLL x y)
214 (Lsh8x(64|32|16|8) x y) && shiftIsBounded(v) => (SHLL x y)
215
216 (Rsh64Ux(64|32|16|8) <t> x y) && !shiftIsBounded(v) => (ANDQ (SHRQ <t> x y) (SBBQcarrymask <t> (CMP(Q|L|W|B)const y [64])))
217 (Rsh32Ux(64|32|16|8) <t> x y) && !shiftIsBounded(v) => (ANDL (SHRL <t> x y) (SBBLcarrymask <t> (CMP(Q|L|W|B)const y [32])))
218 (Rsh16Ux(64|32|16|8) <t> x y) && !shiftIsBounded(v) => (ANDL (SHRW <t> x y) (SBBLcarrymask <t> (CMP(Q|L|W|B)const y [16])))
219 (Rsh8Ux(64|32|16|8) <t> x y) && !shiftIsBounded(v) => (ANDL (SHRB <t> x y) (SBBLcarrymask <t> (CMP(Q|L|W|B)const y [8])))
220
221 (Rsh64Ux(64|32|16|8) x y) && shiftIsBounded(v) => (SHRQ x y)
222 (Rsh32Ux(64|32|16|8) x y) && shiftIsBounded(v) => (SHRL x y)
223 (Rsh16Ux(64|32|16|8) x y) && shiftIsBounded(v) => (SHRW x y)
224 (Rsh8Ux(64|32|16|8) x y) && shiftIsBounded(v) => (SHRB x y)
225
226 // Signed right shift needs to return 0/-1 if shift amount is >= width of shifted value.
227 // We implement this by setting the shift value to -1 (all ones) if the shift value is >= width.
228 (Rsh64x(64|32|16|8) <t> x y) && !shiftIsBounded(v) => (SARQ <t> x (OR(Q|L|L|L) <y.Type> y (NOT(Q|L|L|L) <y.Type> (SBB(Q|L|L|L)carrymask <y.Type> (CMP(Q|L|W|B)const y [64])))))
229 (Rsh32x(64|32|16|8) <t> x y) && !shiftIsBounded(v) => (SARL <t> x (OR(Q|L|L|L) <y.Type> y (NOT(Q|L|L|L) <y.Type> (SBB(Q|L|L|L)carrymask <y.Type> (CMP(Q|L|W|B)const y [32])))))
230 (Rsh16x(64|32|16|8) <t> x y) && !shiftIsBounded(v) => (SARW <t> x (OR(Q|L|L|L) <y.Type> y (NOT(Q|L|L|L) <y.Type> (SBB(Q|L|L|L)carrymask <y.Type> (CMP(Q|L|W|B)const y [16])))))
231 (Rsh8x(64|32|16|8) <t> x y) && !shiftIsBounded(v) => (SARB <t> x (OR(Q|L|L|L) <y.Type> y (NOT(Q|L|L|L) <y.Type> (SBB(Q|L|L|L)carrymask <y.Type> (CMP(Q|L|W|B)const y [8])))))
232
233 (Rsh64x(64|32|16|8) x y) && shiftIsBounded(v) => (SARQ x y)
234 (Rsh32x(64|32|16|8) x y) && shiftIsBounded(v) => (SARL x y)
235 (Rsh16x(64|32|16|8) x y) && shiftIsBounded(v) => (SARW x y)
236 (Rsh8x(64|32|16|8) x y) && shiftIsBounded(v) => (SARB x y)
237
238 // Lowering integer comparisons
239 (Less(64|32|16|8) x y) => (SETL (CMP(Q|L|W|B) x y))
240 (Less(64|32|16|8)U x y) => (SETB (CMP(Q|L|W|B) x y))
241 (Leq(64|32|16|8) x y) => (SETLE (CMP(Q|L|W|B) x y))
242 (Leq(64|32|16|8)U x y) => (SETBE (CMP(Q|L|W|B) x y))
243 (Eq(Ptr|64|32|16|8|B) x y) => (SETEQ (CMP(Q|Q|L|W|B|B) x y))
244 (Neq(Ptr|64|32|16|8|B) x y) => (SETNE (CMP(Q|Q|L|W|B|B) x y))
245
246 // Lowering floating point comparisons
247 // Note Go assembler gets UCOMISx operand order wrong, but it is right here
248 // and the operands are reversed when generating assembly language.
249 (Eq(32|64)F x y) => (SETEQF (UCOMIS(S|D) x y))
250 (Neq(32|64)F x y) => (SETNEF (UCOMIS(S|D) x y))
251 // Use SETGF/SETGEF with reversed operands to dodge NaN case.
252 (Less(32|64)F x y) => (SETGF (UCOMIS(S|D) y x))
253 (Leq(32|64)F x y) => (SETGEF (UCOMIS(S|D) y x))
254
255 // Lowering loads
256 (Load <t> ptr mem) && (is64BitInt(t) || isPtr(t)) => (MOVQload ptr mem)
257 (Load <t> ptr mem) && is32BitInt(t) => (MOVLload ptr mem)
258 (Load <t> ptr mem) && is16BitInt(t) => (MOVWload ptr mem)
259 (Load <t> ptr mem) && (t.IsBoolean() || is8BitInt(t)) => (MOVBload ptr mem)
260 (Load <t> ptr mem) && is32BitFloat(t) => (MOVSSload ptr mem)
261 (Load <t> ptr mem) && is64BitFloat(t) => (MOVSDload ptr mem)
262
263 // Lowering stores
264 (Store {t} ptr val mem) && t.Size() == 8 && t.IsFloat() => (MOVSDstore ptr val mem)
265 (Store {t} ptr val mem) && t.Size() == 4 && t.IsFloat() => (MOVSSstore ptr val mem)
266 (Store {t} ptr val mem) && t.Size() == 8 && !t.IsFloat() => (MOVQstore ptr val mem)
267 (Store {t} ptr val mem) && t.Size() == 4 && !t.IsFloat() => (MOVLstore ptr val mem)
268 (Store {t} ptr val mem) && t.Size() == 2 => (MOVWstore ptr val mem)
269 (Store {t} ptr val mem) && t.Size() == 1 => (MOVBstore ptr val mem)
270
271 // Lowering moves
272 (Move [0] _ _ mem) => mem
273 (Move [1] dst src mem) => (MOVBstore dst (MOVBload src mem) mem)
274 (Move [2] dst src mem) => (MOVWstore dst (MOVWload src mem) mem)
275 (Move [4] dst src mem) => (MOVLstore dst (MOVLload src mem) mem)
276 (Move [8] dst src mem) => (MOVQstore dst (MOVQload src mem) mem)
277 (Move [16] dst src mem) => (MOVOstore dst (MOVOload src mem) mem)
278
279 (Move [3] dst src mem) =>
280 (MOVBstore [2] dst (MOVBload [2] src mem)
281 (MOVWstore dst (MOVWload src mem) mem))
282 (Move [5] dst src mem) =>
283 (MOVBstore [4] dst (MOVBload [4] src mem)
284 (MOVLstore dst (MOVLload src mem) mem))
285 (Move [6] dst src mem) =>
286 (MOVWstore [4] dst (MOVWload [4] src mem)
287 (MOVLstore dst (MOVLload src mem) mem))
288 (Move [7] dst src mem) =>
289 (MOVLstore [3] dst (MOVLload [3] src mem)
290 (MOVLstore dst (MOVLload src mem) mem))
291 (Move [9] dst src mem) =>
292 (MOVBstore [8] dst (MOVBload [8] src mem)
293 (MOVQstore dst (MOVQload src mem) mem))
294 (Move [10] dst src mem) =>
295 (MOVWstore [8] dst (MOVWload [8] src mem)
296 (MOVQstore dst (MOVQload src mem) mem))
297 (Move [11] dst src mem) =>
298 (MOVLstore [7] dst (MOVLload [7] src mem)
299 (MOVQstore dst (MOVQload src mem) mem))
300 (Move [12] dst src mem) =>
301 (MOVLstore [8] dst (MOVLload [8] src mem)
302 (MOVQstore dst (MOVQload src mem) mem))
303 (Move [s] dst src mem) && s >= 13 && s <= 15 =>
304 (MOVQstore [int32(s-8)] dst (MOVQload [int32(s-8)] src mem)
305 (MOVQstore dst (MOVQload src mem) mem))
306
307 // Copying up to 192 bytes uses straightline code.
308 (Move [s] dst src mem) && s > 16 && s < 192 && logLargeCopy(v, s) => (LoweredMove [s] dst src mem)
309
310 // Copying up to ~1KB uses a small loop.
311 (Move [s] dst src mem) && s >= 192 && s <= repMoveThreshold && logLargeCopy(v, s) => (LoweredMoveLoop [s] dst src mem)
312
313 // Large copying uses REP MOVSQ.
314 (Move [s] dst src mem) && s > repMoveThreshold && s%8 != 0 =>
315 (Move [s-s%8]
316 (OffPtr <dst.Type> dst [s%8])
317 (OffPtr <src.Type> src [s%8])
318 (MOVQstore dst (MOVQload src mem) mem))
319 (Move [s] dst src mem) && s > repMoveThreshold && s%8 == 0 && logLargeCopy(v, s) =>
320 (REPMOVSQ dst src (MOVQconst [s/8]) mem)
321
322 // Lowering Zero instructions
323 (Zero [0] _ mem) => mem
324 (Zero [1] destptr mem) => (MOVBstoreconst [makeValAndOff(0,0)] destptr mem)
325 (Zero [2] destptr mem) => (MOVWstoreconst [makeValAndOff(0,0)] destptr mem)
326 (Zero [4] destptr mem) => (MOVLstoreconst [makeValAndOff(0,0)] destptr mem)
327 (Zero [8] destptr mem) => (MOVQstoreconst [makeValAndOff(0,0)] destptr mem)
328
329 (Zero [3] destptr mem) =>
330 (MOVBstoreconst [makeValAndOff(0,2)] destptr
331 (MOVWstoreconst [makeValAndOff(0,0)] destptr mem))
332 (Zero [5] destptr mem) =>
333 (MOVBstoreconst [makeValAndOff(0,4)] destptr
334 (MOVLstoreconst [makeValAndOff(0,0)] destptr mem))
335 (Zero [6] destptr mem) =>
336 (MOVWstoreconst [makeValAndOff(0,4)] destptr
337 (MOVLstoreconst [makeValAndOff(0,0)] destptr mem))
338 (Zero [7] destptr mem) =>
339 (MOVLstoreconst [makeValAndOff(0,3)] destptr
340 (MOVLstoreconst [makeValAndOff(0,0)] destptr mem))
341
342 // Zero small numbers of words directly.
343 (Zero [9] destptr mem) =>
344 (MOVBstoreconst [makeValAndOff(0,8)] destptr
345 (MOVQstoreconst [makeValAndOff(0,0)] destptr mem))
346
347 (Zero [10] destptr mem) =>
348 (MOVWstoreconst [makeValAndOff(0,8)] destptr
349 (MOVQstoreconst [makeValAndOff(0,0)] destptr mem))
350
351 (Zero [11] destptr mem) =>
352 (MOVLstoreconst [makeValAndOff(0,7)] destptr
353 (MOVQstoreconst [makeValAndOff(0,0)] destptr mem))
354
355 (Zero [12] destptr mem) =>
356 (MOVLstoreconst [makeValAndOff(0,8)] destptr
357 (MOVQstoreconst [makeValAndOff(0,0)] destptr mem))
358
359 (Zero [s] destptr mem) && s > 12 && s < 16 =>
360 (MOVQstoreconst [makeValAndOff(0,int32(s-8))] destptr
361 (MOVQstoreconst [makeValAndOff(0,0)] destptr mem))
362
363 // Zeroing up to 192 bytes uses straightline code.
364 (Zero [s] destptr mem) && s >= 16 && s < 192 => (LoweredZero [s] destptr mem)
365
366 // Zeroing up to ~1KB uses a small loop.
367 (Zero [s] destptr mem) && s >= 192 && s <= repZeroThreshold => (LoweredZeroLoop [s] destptr mem)
368
369 // Large zeroing uses REP STOSQ.
370 (Zero [s] destptr mem) && s > repZeroThreshold && s%8 != 0 =>
371 (Zero [s-s%8] (OffPtr <destptr.Type> destptr [s%8])
372 (MOVOstoreconst [makeValAndOff(0,0)] destptr mem))
373 (Zero [s] destptr mem) && s > repZeroThreshold && s%8 == 0 =>
374 (REPSTOSQ destptr (MOVQconst [s/8]) (MOVQconst [0]) mem)
375
376 // Lowering constants
377 (Const8 [c]) => (MOVLconst [int32(c)])
378 (Const16 [c]) => (MOVLconst [int32(c)])
379 (Const32 ...) => (MOVLconst ...)
380 (Const64 ...) => (MOVQconst ...)
381 (Const32F ...) => (MOVSSconst ...)
382 (Const64F ...) => (MOVSDconst ...)
383 (ConstNil ) => (MOVQconst [0])
384 (ConstBool [c]) => (MOVLconst [b2i32(c)])
385
386 // Lowering calls
387 (StaticCall ...) => (CALLstatic ...)
388 (ClosureCall ...) => (CALLclosure ...)
389 (InterCall ...) => (CALLinter ...)
390 (TailCall ...) => (CALLtail ...)
391 (TailCallInter ...) => (CALLtailinter ...)
392
393 // Lowering conditional moves
394 // If the condition is a SETxx, we can just run a CMOV from the comparison that was
395 // setting the flags.
396 // Legend: HI=unsigned ABOVE, CS=unsigned BELOW, CC=unsigned ABOVE EQUAL, LS=unsigned BELOW EQUAL
397 (CondSelect <t> x y (SET(EQ|NE|L|G|LE|GE|A|B|AE|BE|EQF|NEF|GF|GEF) cond)) && (is64BitInt(t) || isPtr(t))
398 => (CMOVQ(EQ|NE|LT|GT|LE|GE|HI|CS|CC|LS|EQF|NEF|GTF|GEF) y x cond)
399 (CondSelect <t> x y (SET(EQ|NE|L|G|LE|GE|A|B|AE|BE|EQF|NEF|GF|GEF) cond)) && is32BitInt(t)
400 => (CMOVL(EQ|NE|LT|GT|LE|GE|HI|CS|CC|LS|EQF|NEF|GTF|GEF) y x cond)
401 (CondSelect <t> x y (SET(EQ|NE|L|G|LE|GE|A|B|AE|BE|EQF|NEF|GF|GEF) cond)) && is16BitInt(t)
402 => (CMOVW(EQ|NE|LT|GT|LE|GE|HI|CS|CC|LS|EQF|NEF|GTF|GEF) y x cond)
403
404 (CondSelect <t> x y check) && !check.Type.IsFlags() && check.Type.Size() == 8 && (is64BitInt(t) || isPtr(t))
405 => (CMOVQNE y x (CMPQconst [0] check))
406 (CondSelect <t> x y check) && !check.Type.IsFlags() && check.Type.Size() == 8 && is32BitInt(t)
407 => (CMOVLNE y x (CMPQconst [0] check))
408 (CondSelect <t> x y check) && !check.Type.IsFlags() && check.Type.Size() == 8 && is16BitInt(t)
409 => (CMOVWNE y x (CMPQconst [0] check))
410 (CondSelect <t> x y check) && !check.Type.IsFlags() && check.Type.Size() == 4 && (is64BitInt(t) || isPtr(t))
411 => (CMOVQNE y x (CMPLconst [0] check))
412 (CondSelect <t> x y check) && !check.Type.IsFlags() && check.Type.Size() == 4 && is32BitInt(t)
413 => (CMOVLNE y x (CMPLconst [0] check))
414 (CondSelect <t> x y check) && !check.Type.IsFlags() && check.Type.Size() == 4 && is16BitInt(t)
415 => (CMOVWNE y x (CMPLconst [0] check))
416 (CondSelect <t> x y check) && !check.Type.IsFlags() && check.Type.Size() == 2 && (is64BitInt(t) || isPtr(t))
417 => (CMOVQNE y x (CMPWconst [0] check))
418 (CondSelect <t> x y check) && !check.Type.IsFlags() && check.Type.Size() == 2 && is32BitInt(t)
419 => (CMOVLNE y x (CMPWconst [0] check))
420 (CondSelect <t> x y check) && !check.Type.IsFlags() && check.Type.Size() == 2 && is16BitInt(t)
421 => (CMOVWNE y x (CMPWconst [0] check))
422 (CondSelect <t> x y check) && !check.Type.IsFlags() && check.Type.Size() == 1 && (is64BitInt(t) || isPtr(t))
423 => (CMOVQNE y x (CMPBconst [0] check))
424 (CondSelect <t> x y check) && !check.Type.IsFlags() && check.Type.Size() == 1 && is32BitInt(t)
425 => (CMOVLNE y x (CMPBconst [0] check))
426 (CondSelect <t> x y check) && !check.Type.IsFlags() && check.Type.Size() == 1 && is16BitInt(t)
427 => (CMOVWNE y x (CMPBconst [0] check))
428
429 // Absorb InvertFlags
430 (CMOVQ(EQ|NE|LT|GT|LE|GE|HI|CS|CC|LS) x y (InvertFlags cond))
431 => (CMOVQ(EQ|NE|GT|LT|GE|LE|CS|HI|LS|CC) x y cond)
432 (CMOVL(EQ|NE|LT|GT|LE|GE|HI|CS|CC|LS) x y (InvertFlags cond))
433 => (CMOVL(EQ|NE|GT|LT|GE|LE|CS|HI|LS|CC) x y cond)
434 (CMOVW(EQ|NE|LT|GT|LE|GE|HI|CS|CC|LS) x y (InvertFlags cond))
435 => (CMOVW(EQ|NE|GT|LT|GE|LE|CS|HI|LS|CC) x y cond)
436
437 // Absorb constants generated during lower
438 (CMOV(QEQ|QLE|QGE|QCC|QLS|LEQ|LLE|LGE|LCC|LLS|WEQ|WLE|WGE|WCC|WLS) _ x (FlagEQ)) => x
439 (CMOV(QNE|QLT|QGT|QCS|QHI|LNE|LLT|LGT|LCS|LHI|WNE|WLT|WGT|WCS|WHI) y _ (FlagEQ)) => y
440 (CMOV(QNE|QGT|QGE|QHI|QCC|LNE|LGT|LGE|LHI|LCC|WNE|WGT|WGE|WHI|WCC) _ x (FlagGT_UGT)) => x
441 (CMOV(QEQ|QLE|QLT|QLS|QCS|LEQ|LLE|LLT|LLS|LCS|WEQ|WLE|WLT|WLS|WCS) y _ (FlagGT_UGT)) => y
442 (CMOV(QNE|QGT|QGE|QLS|QCS|LNE|LGT|LGE|LLS|LCS|WNE|WGT|WGE|WLS|WCS) _ x (FlagGT_ULT)) => x
443 (CMOV(QEQ|QLE|QLT|QHI|QCC|LEQ|LLE|LLT|LHI|LCC|WEQ|WLE|WLT|WHI|WCC) y _ (FlagGT_ULT)) => y
444 (CMOV(QNE|QLT|QLE|QCS|QLS|LNE|LLT|LLE|LCS|LLS|WNE|WLT|WLE|WCS|WLS) _ x (FlagLT_ULT)) => x
445 (CMOV(QEQ|QGT|QGE|QHI|QCC|LEQ|LGT|LGE|LHI|LCC|WEQ|WGT|WGE|WHI|WCC) y _ (FlagLT_ULT)) => y
446 (CMOV(QNE|QLT|QLE|QHI|QCC|LNE|LLT|LLE|LHI|LCC|WNE|WLT|WLE|WHI|WCC) _ x (FlagLT_UGT)) => x
447 (CMOV(QEQ|QGT|QGE|QCS|QLS|LEQ|LGT|LGE|LCS|LLS|WEQ|WGT|WGE|WCS|WLS) y _ (FlagLT_UGT)) => y
448
449 // Miscellaneous
450 (IsNonNil p) => (SETNE (TESTQ p p))
451 (IsInBounds idx len) => (SETB (CMPQ idx len))
452 (IsSliceInBounds idx len) => (SETBE (CMPQ idx len))
453 (NilCheck ...) => (LoweredNilCheck ...)
454 (GetG mem) && v.Block.Func.OwnAux.Fn.ABI() != obj.ABIInternal => (LoweredGetG mem) // only lower in old ABI. in new ABI we have a G register.
455 (GetClosurePtr ...) => (LoweredGetClosurePtr ...)
456 (GetCallerPC ...) => (LoweredGetCallerPC ...)
457 (GetCallerSP ...) => (LoweredGetCallerSP ...)
458
459 (HasCPUFeature {s}) => (SETNE (CMPLconst [0] (LoweredHasCPUFeature {s})))
460 (Addr {sym} base) => (LEAQ {sym} base)
461 (LocalAddr <t> {sym} base mem) && t.Elem().HasPointers() => (LEAQ {sym} (SPanchored base mem))
462 (LocalAddr <t> {sym} base _) && !t.Elem().HasPointers() => (LEAQ {sym} base)
463
464 (MOVBstore [off] {sym} ptr y:(SETL x) mem) && y.Uses == 1 => (SETLstore [off] {sym} ptr x mem)
465 (MOVBstore [off] {sym} ptr y:(SETLE x) mem) && y.Uses == 1 => (SETLEstore [off] {sym} ptr x mem)
466 (MOVBstore [off] {sym} ptr y:(SETG x) mem) && y.Uses == 1 => (SETGstore [off] {sym} ptr x mem)
467 (MOVBstore [off] {sym} ptr y:(SETGE x) mem) && y.Uses == 1 => (SETGEstore [off] {sym} ptr x mem)
468 (MOVBstore [off] {sym} ptr y:(SETEQ x) mem) && y.Uses == 1 => (SETEQstore [off] {sym} ptr x mem)
469 (MOVBstore [off] {sym} ptr y:(SETNE x) mem) && y.Uses == 1 => (SETNEstore [off] {sym} ptr x mem)
470 (MOVBstore [off] {sym} ptr y:(SETB x) mem) && y.Uses == 1 => (SETBstore [off] {sym} ptr x mem)
471 (MOVBstore [off] {sym} ptr y:(SETBE x) mem) && y.Uses == 1 => (SETBEstore [off] {sym} ptr x mem)
472 (MOVBstore [off] {sym} ptr y:(SETA x) mem) && y.Uses == 1 => (SETAstore [off] {sym} ptr x mem)
473 (MOVBstore [off] {sym} ptr y:(SETAE x) mem) && y.Uses == 1 => (SETAEstore [off] {sym} ptr x mem)
474
475 // block rewrites
476 (If (SETL cmp) yes no) => (LT cmp yes no)
477 (If (SETLE cmp) yes no) => (LE cmp yes no)
478 (If (SETG cmp) yes no) => (GT cmp yes no)
479 (If (SETGE cmp) yes no) => (GE cmp yes no)
480 (If (SETEQ cmp) yes no) => (EQ cmp yes no)
481 (If (SETNE cmp) yes no) => (NE cmp yes no)
482 (If (SETB cmp) yes no) => (ULT cmp yes no)
483 (If (SETBE cmp) yes no) => (ULE cmp yes no)
484 (If (SETA cmp) yes no) => (UGT cmp yes no)
485 (If (SETAE cmp) yes no) => (UGE cmp yes no)
486 (If (SETO cmp) yes no) => (OS cmp yes no)
487
488 // Special case for floating point - LF/LEF not generated
489 (If (SETGF cmp) yes no) => (UGT cmp yes no)
490 (If (SETGEF cmp) yes no) => (UGE cmp yes no)
491 (If (SETEQF cmp) yes no) => (EQF cmp yes no)
492 (If (SETNEF cmp) yes no) => (NEF cmp yes no)
493
494 (If cond yes no) => (NE (TESTB cond cond) yes no)
495
496 (JumpTable idx) => (JUMPTABLE {makeJumpTableSym(b)} idx (LEAQ <typ.Uintptr> {makeJumpTableSym(b)} (SB)))
497
498 // Atomic loads. Other than preserving their ordering with respect to other loads, nothing special here.
499 (AtomicLoad8 ptr mem) => (MOVBatomicload ptr mem)
500 (AtomicLoad32 ptr mem) => (MOVLatomicload ptr mem)
501 (AtomicLoad64 ptr mem) => (MOVQatomicload ptr mem)
502 (AtomicLoadPtr ptr mem) => (MOVQatomicload ptr mem)
503
504 // Atomic stores. We use XCHG to prevent the hardware reordering a subsequent load.
505 // TODO: most runtime uses of atomic stores don't need that property. Use normal stores for those?
506 (AtomicStore8 ptr val mem) => (Select1 (XCHGB <types.NewTuple(typ.UInt8,types.TypeMem)> val ptr mem))
507 (AtomicStore32 ptr val mem) => (Select1 (XCHGL <types.NewTuple(typ.UInt32,types.TypeMem)> val ptr mem))
508 (AtomicStore64 ptr val mem) => (Select1 (XCHGQ <types.NewTuple(typ.UInt64,types.TypeMem)> val ptr mem))
509 (AtomicStorePtrNoWB ptr val mem) => (Select1 (XCHGQ <types.NewTuple(typ.BytePtr,types.TypeMem)> val ptr mem))
510
511 // Atomic exchanges.
512 (AtomicExchange8 ptr val mem) => (XCHGB val ptr mem)
513 (AtomicExchange32 ptr val mem) => (XCHGL val ptr mem)
514 (AtomicExchange64 ptr val mem) => (XCHGQ val ptr mem)
515
516 // Atomic adds.
517 (AtomicAdd32 ptr val mem) => (AddTupleFirst32 val (XADDLlock val ptr mem))
518 (AtomicAdd64 ptr val mem) => (AddTupleFirst64 val (XADDQlock val ptr mem))
519 (Select0 <t> (AddTupleFirst32 val tuple)) => (ADDL val (Select0 <t> tuple))
520 (Select1 (AddTupleFirst32 _ tuple)) => (Select1 tuple)
521 (Select0 <t> (AddTupleFirst64 val tuple)) => (ADDQ val (Select0 <t> tuple))
522 (Select1 (AddTupleFirst64 _ tuple)) => (Select1 tuple)
523
524 // Atomic compare and swap.
525 (AtomicCompareAndSwap32 ptr old new_ mem) => (CMPXCHGLlock ptr old new_ mem)
526 (AtomicCompareAndSwap64 ptr old new_ mem) => (CMPXCHGQlock ptr old new_ mem)
527
528 // Atomic memory logical operations (old style).
529 (AtomicAnd8 ptr val mem) => (ANDBlock ptr val mem)
530 (AtomicAnd32 ptr val mem) => (ANDLlock ptr val mem)
531 (AtomicOr8 ptr val mem) => (ORBlock ptr val mem)
532 (AtomicOr32 ptr val mem) => (ORLlock ptr val mem)
533
534 // Atomic memory logical operations (new style).
535 (Atomic(And64|And32|Or64|Or32)value ptr val mem) => (LoweredAtomic(And64|And32|Or64|Or32) ptr val mem)
536
537 // Write barrier.
538 (WB ...) => (LoweredWB ...)
539
540 (PanicBounds ...) => (LoweredPanicBoundsRR ...)
541 (LoweredPanicBoundsRR [kind] x (MOVQconst [c]) mem) => (LoweredPanicBoundsRC [kind] x {PanicBoundsC{C:c}} mem)
542 (LoweredPanicBoundsRR [kind] (MOVQconst [c]) y mem) => (LoweredPanicBoundsCR [kind] {PanicBoundsC{C:c}} y mem)
543 (LoweredPanicBoundsRC [kind] {p} (MOVQconst [c]) mem) => (LoweredPanicBoundsCC [kind] {PanicBoundsCC{Cx:c, Cy:p.C}} mem)
544 (LoweredPanicBoundsCR [kind] {p} (MOVQconst [c]) mem) => (LoweredPanicBoundsCC [kind] {PanicBoundsCC{Cx:p.C, Cy:c}} mem)
545
546 // lowering rotates
547 (RotateLeft8 ...) => (ROLB ...)
548 (RotateLeft16 ...) => (ROLW ...)
549 (RotateLeft32 ...) => (ROLL ...)
550 (RotateLeft64 ...) => (ROLQ ...)
551
552 // ***************************
553 // Above: lowering rules
554 // Below: optimizations
555 // ***************************
556 // TODO: Should the optimizations be a separate pass?
557
558 // Fold boolean tests into blocks
559 (NE (TESTB (SETL cmp) (SETL cmp)) yes no) => (LT cmp yes no)
560 (NE (TESTB (SETLE cmp) (SETLE cmp)) yes no) => (LE cmp yes no)
561 (NE (TESTB (SETG cmp) (SETG cmp)) yes no) => (GT cmp yes no)
562 (NE (TESTB (SETGE cmp) (SETGE cmp)) yes no) => (GE cmp yes no)
563 (NE (TESTB (SETEQ cmp) (SETEQ cmp)) yes no) => (EQ cmp yes no)
564 (NE (TESTB (SETNE cmp) (SETNE cmp)) yes no) => (NE cmp yes no)
565 (NE (TESTB (SETB cmp) (SETB cmp)) yes no) => (ULT cmp yes no)
566 (NE (TESTB (SETBE cmp) (SETBE cmp)) yes no) => (ULE cmp yes no)
567 (NE (TESTB (SETA cmp) (SETA cmp)) yes no) => (UGT cmp yes no)
568 (NE (TESTB (SETAE cmp) (SETAE cmp)) yes no) => (UGE cmp yes no)
569 (NE (TESTB (SETO cmp) (SETO cmp)) yes no) => (OS cmp yes no)
570
571 // Unsigned comparisons to 0/1
572 (ULT (TEST(Q|L|W|B) x x) yes no) => (First no yes)
573 (UGE (TEST(Q|L|W|B) x x) yes no) => (First yes no)
574 (SETB (TEST(Q|L|W|B) x x)) => (ConstBool [false])
575 (SETAE (TEST(Q|L|W|B) x x)) => (ConstBool [true])
576
577 // x & 1 != 0 -> x & 1
578 (SETNE (TEST(B|W)const [1] x)) => (AND(L|L)const [1] x)
579 (SETB (BT(L|Q)const [0] x)) => (AND(L|Q)const [1] x)
580 // x & 1 == 0 -> (x & 1) ^ 1
581 (SETAE (BT(L|Q)const [0] x)) => (XORLconst [1] (ANDLconst <typ.Bool> [1] x))
582
583 // Shorten compare by rewriting x < 128 as x <= 127, which can be encoded in a single-byte immediate on x86.
584 (SETL c:(CMP(Q|L)const [128] x)) && c.Uses == 1 => (SETLE (CMP(Q|L)const [127] x))
585 (SETB c:(CMP(Q|L)const [128] x)) && c.Uses == 1 => (SETBE (CMP(Q|L)const [127] x))
586
587 // x >= 128 -> x > 127
588 (SETGE c:(CMP(Q|L)const [128] x)) && c.Uses == 1 => (SETG (CMP(Q|L)const [127] x))
589 (SETAE c:(CMP(Q|L)const [128] x)) && c.Uses == 1 => (SETA (CMP(Q|L)const [127] x))
590
591 (CMOVQLT x y c:(CMP(Q|L)const [128] z)) && c.Uses == 1 => (CMOVQLE x y (CMP(Q|L)const [127] z))
592 (CMOVLLT x y c:(CMP(Q|L)const [128] z)) && c.Uses == 1 => (CMOVLLE x y (CMP(Q|L)const [127] z))
593 (LT c:(CMP(Q|L)const [128] z) yes no) && c.Uses == 1 => (LE (CMP(Q|L)const [127] z) yes no)
594 (CMOVQGE x y c:(CMP(Q|L)const [128] z)) && c.Uses == 1 => (CMOVQGT x y (CMP(Q|L)const [127] z))
595 (CMOVLGE x y c:(CMP(Q|L)const [128] z)) && c.Uses == 1 => (CMOVLGT x y (CMP(Q|L)const [127] z))
596 (GE c:(CMP(Q|L)const [128] z) yes no) && c.Uses == 1 => (GT (CMP(Q|L)const [127] z) yes no)
597
598 // Recognize bit tests: a&(1<<b) != 0 for b suitably bounded
599 // Note that BTx instructions use the carry bit, so we need to convert tests for zero flag
600 // into tests for carry flags.
601 // ULT and SETB check the carry flag; they are identical to CS and SETCS. Same, mutatis
602 // mutandis, for UGE and SETAE, and CC and SETCC.
603 ((NE|EQ) (TESTL (SHLL (MOVLconst [1]) x) y)) => ((ULT|UGE) (BTL x y))
604 ((NE|EQ) (TESTQ (SHLQ (MOVQconst [1]) x) y)) => ((ULT|UGE) (BTQ x y))
605 ((NE|EQ) (TESTLconst [c] x)) && isPowerOfTwo(uint32(c))
606 => ((ULT|UGE) (BTLconst [int8(log32u(uint32(c)))] x))
607 ((NE|EQ) (TESTQconst [c] x)) && isPowerOfTwo(uint64(c))
608 => ((ULT|UGE) (BTQconst [int8(log32u(uint32(c)))] x))
609 ((NE|EQ) (TESTQ (MOVQconst [c]) x)) && isPowerOfTwo(uint64(c))
610 => ((ULT|UGE) (BTQconst [int8(log64u(uint64(c)))] x))
611 (SET(NE|EQ) (TESTL (SHLL (MOVLconst [1]) x) y)) => (SET(B|AE) (BTL x y))
612 (SET(NE|EQ) (TESTQ (SHLQ (MOVQconst [1]) x) y)) => (SET(B|AE) (BTQ x y))
613 (SET(NE|EQ) (TESTLconst [c] x)) && isPowerOfTwo(uint32(c))
614 => (SET(B|AE) (BTLconst [int8(log32u(uint32(c)))] x))
615 (SET(NE|EQ) (TESTQconst [c] x)) && isPowerOfTwo(uint64(c))
616 => (SET(B|AE) (BTQconst [int8(log32u(uint32(c)))] x))
617 (SET(NE|EQ) (TESTQ (MOVQconst [c]) x)) && isPowerOfTwo(uint64(c))
618 => (SET(B|AE) (BTQconst [int8(log64u(uint64(c)))] x))
619 // SET..store variant
620 (SET(NE|EQ)store [off] {sym} ptr (TESTL (SHLL (MOVLconst [1]) x) y) mem)
621 => (SET(B|AE)store [off] {sym} ptr (BTL x y) mem)
622 (SET(NE|EQ)store [off] {sym} ptr (TESTQ (SHLQ (MOVQconst [1]) x) y) mem)
623 => (SET(B|AE)store [off] {sym} ptr (BTQ x y) mem)
624 (SET(NE|EQ)store [off] {sym} ptr (TESTLconst [c] x) mem) && isPowerOfTwo(uint32(c))
625 => (SET(B|AE)store [off] {sym} ptr (BTLconst [int8(log32u(uint32(c)))] x) mem)
626 (SET(NE|EQ)store [off] {sym} ptr (TESTQconst [c] x) mem) && isPowerOfTwo(uint64(c))
627 => (SET(B|AE)store [off] {sym} ptr (BTQconst [int8(log32u(uint32(c)))] x) mem)
628 (SET(NE|EQ)store [off] {sym} ptr (TESTQ (MOVQconst [c]) x) mem) && isPowerOfTwo(uint64(c))
629 => (SET(B|AE)store [off] {sym} ptr (BTQconst [int8(log64u(uint64(c)))] x) mem)
630
631 // Handle bit-testing in the form (a>>b)&1 != 0 by building the above rules
632 // and further combining shifts.
633 (BT(Q|L)const [c] (SHRQconst [d] x)) && (c+d)<64 => (BTQconst [c+d] x)
634 (BT(Q|L)const [c] (ADDQ x x)) && c>1 => (BT(Q|L)const [c-1] x)
635 (BT(Q|L)const [c] (SHLQconst [d] x)) && c>d => (BT(Q|L)const [c-d] x)
636 (BT(Q|L)const [0] s:(SHRQ x y)) => (BTQ y x)
637 (BTLconst [c] (SHRLconst [d] x)) && (c+d)<32 => (BTLconst [c+d] x)
638 (BTLconst [c] (ADDL x x)) && c>1 => (BTLconst [c-1] x)
639 (BTLconst [c] (SHLLconst [d] x)) && c>d => (BTLconst [c-d] x)
640 (BTLconst [0] s:(SHR(L|XL) x y)) => (BTL y x)
641
642 // Rewrite a & 1 != 1 into a & 1 == 0.
643 // Among other things, this lets us turn (a>>b)&1 != 1 into a bit test.
644 (SET(NE|EQ) (CMPLconst [1] s:(ANDLconst [1] _))) => (SET(EQ|NE) (CMPLconst [0] s))
645 (SET(NE|EQ)store [off] {sym} ptr (CMPLconst [1] s:(ANDLconst [1] _)) mem) => (SET(EQ|NE)store [off] {sym} ptr (CMPLconst [0] s) mem)
646 (SET(NE|EQ) (CMPQconst [1] s:(ANDQconst [1] _))) => (SET(EQ|NE) (CMPQconst [0] s))
647 (SET(NE|EQ)store [off] {sym} ptr (CMPQconst [1] s:(ANDQconst [1] _)) mem) => (SET(EQ|NE)store [off] {sym} ptr (CMPQconst [0] s) mem)
648
649 // Recognize bit setting (a |= 1<<b) and toggling (a ^= 1<<b)
650 (OR(Q|L) (SHL(Q|L) (MOV(Q|L)const [1]) y) x) => (BTS(Q|L) x y)
651 (XOR(Q|L) (SHL(Q|L) (MOV(Q|L)const [1]) y) x) => (BTC(Q|L) x y)
652 // Note: only convert OR/XOR to BTS/BTC if the constant wouldn't fit in
653 // the constant field of the OR/XOR instruction. See issue 61694.
654 ((OR|XOR)Q (MOVQconst [c]) x) && isPowerOfTwo(uint64(c)) && uint64(c) >= 1<<31 => (BT(S|C)Qconst [int8(log64u(uint64(c)))] x)
655
656 // Recognize bit clearing: a &^= 1<<b
657 (AND(Q|L) (NOT(Q|L) (SHL(Q|L) (MOV(Q|L)const [1]) y)) x) => (BTR(Q|L) x y)
658 (ANDN(Q|L) x (SHL(Q|L) (MOV(Q|L)const [1]) y)) => (BTR(Q|L) x y)
659 // Note: only convert AND to BTR if the constant wouldn't fit in
660 // the constant field of the AND instruction. See issue 61694.
661 (ANDQ (MOVQconst [c]) x) && isPowerOfTwo(uint64(^c)) && uint64(^c) >= 1<<31 => (BTRQconst [int8(log64u(uint64(^c)))] x)
662
663 // Special-case bit patterns on first/last bit.
664 // generic.rules changes ANDs of high-part/low-part masks into a couple of shifts,
665 // for instance:
666 // x & 0xFFFF0000 -> (x >> 16) << 16
667 // x & 0x80000000 -> (x >> 31) << 31
668 //
669 // In case the mask is just one bit (like second example above), it conflicts
670 // with the above rules to detect bit-testing / bit-clearing of first/last bit.
671 // We thus special-case them, by detecting the shift patterns.
672
673 // Special case resetting first/last bit
674 (ADD(L|Q) (SHR(L|Q)const [1] x) (SHR(L|Q)const [1] x))
675 => (AND(L|Q)const [-2] x)
676 (SHRLconst [1] (ADDL x x))
677 => (ANDLconst [0x7fffffff] x)
678 (SHRQconst [1] (ADDQ x x))
679 => (BTRQconst [63] x)
680
681 // Special case testing first/last bit (with double-shift generated by generic.rules)
682 ((SETNE|SETEQ|NE|EQ) (TESTQ z1:(SHLQconst [63] (SHRQconst [63] x)) z2)) && z1==z2
683 => ((SETB|SETAE|ULT|UGE) (BTQconst [63] x))
684 ((SETNE|SETEQ|NE|EQ) (TESTL z1:(SHLLconst [31] (SHRQconst [31] x)) z2)) && z1==z2
685 => ((SETB|SETAE|ULT|UGE) (BTQconst [31] x))
686 (SET(NE|EQ)store [off] {sym} ptr (TESTQ z1:(SHLQconst [63] (SHRQconst [63] x)) z2) mem) && z1==z2
687 => (SET(B|AE)store [off] {sym} ptr (BTQconst [63] x) mem)
688 (SET(NE|EQ)store [off] {sym} ptr (TESTL z1:(SHLLconst [31] (SHRLconst [31] x)) z2) mem) && z1==z2
689 => (SET(B|AE)store [off] {sym} ptr (BTLconst [31] x) mem)
690
691 ((SETNE|SETEQ|NE|EQ) (TESTQ z1:(SHRQconst [63] (SHLQconst [63] x)) z2)) && z1==z2
692 => ((SETB|SETAE|ULT|UGE) (BTQconst [0] x))
693 ((SETNE|SETEQ|NE|EQ) (TESTL z1:(SHRLconst [31] (SHLLconst [31] x)) z2)) && z1==z2
694 => ((SETB|SETAE|ULT|UGE) (BTLconst [0] x))
695 (SET(NE|EQ)store [off] {sym} ptr (TESTQ z1:(SHRQconst [63] (SHLQconst [63] x)) z2) mem) && z1==z2
696 => (SET(B|AE)store [off] {sym} ptr (BTQconst [0] x) mem)
697 (SET(NE|EQ)store [off] {sym} ptr (TESTL z1:(SHRLconst [31] (SHLLconst [31] x)) z2) mem) && z1==z2
698 => (SET(B|AE)store [off] {sym} ptr (BTLconst [0] x) mem)
699
700 // Special-case manually testing last bit with "a>>63 != 0" (without "&1")
701 ((SETNE|SETEQ|NE|EQ) (TESTQ z1:(SHRQconst [63] x) z2)) && z1==z2
702 => ((SETB|SETAE|ULT|UGE) (BTQconst [63] x))
703 ((SETNE|SETEQ|NE|EQ) (TESTL z1:(SHRLconst [31] x) z2)) && z1==z2
704 => ((SETB|SETAE|ULT|UGE) (BTLconst [31] x))
705 (SET(NE|EQ)store [off] {sym} ptr (TESTQ z1:(SHRQconst [63] x) z2) mem) && z1==z2
706 => (SET(B|AE)store [off] {sym} ptr (BTQconst [63] x) mem)
707 (SET(NE|EQ)store [off] {sym} ptr (TESTL z1:(SHRLconst [31] x) z2) mem) && z1==z2
708 => (SET(B|AE)store [off] {sym} ptr (BTLconst [31] x) mem)
709
710 // Fold combinations of bit ops on same bit. An example is math.Copysign(c,-1)
711 (BTSQconst [c] (BTRQconst [c] x)) => (BTSQconst [c] x)
712 (BTSQconst [c] (BTCQconst [c] x)) => (BTSQconst [c] x)
713 (BTRQconst [c] (BTSQconst [c] x)) => (BTRQconst [c] x)
714 (BTRQconst [c] (BTCQconst [c] x)) => (BTRQconst [c] x)
715
716 // Fold boolean negation into SETcc.
717 (XORLconst [1] (SETNE x)) => (SETEQ x)
718 (XORLconst [1] (SETEQ x)) => (SETNE x)
719 (XORLconst [1] (SETL x)) => (SETGE x)
720 (XORLconst [1] (SETGE x)) => (SETL x)
721 (XORLconst [1] (SETLE x)) => (SETG x)
722 (XORLconst [1] (SETG x)) => (SETLE x)
723 (XORLconst [1] (SETB x)) => (SETAE x)
724 (XORLconst [1] (SETAE x)) => (SETB x)
725 (XORLconst [1] (SETBE x)) => (SETA x)
726 (XORLconst [1] (SETA x)) => (SETBE x)
727
728 // Special case for floating point - LF/LEF not generated
729 (NE (TESTB (SETGF cmp) (SETGF cmp)) yes no) => (UGT cmp yes no)
730 (NE (TESTB (SETGEF cmp) (SETGEF cmp)) yes no) => (UGE cmp yes no)
731 (NE (TESTB (SETEQF cmp) (SETEQF cmp)) yes no) => (EQF cmp yes no)
732 (NE (TESTB (SETNEF cmp) (SETNEF cmp)) yes no) => (NEF cmp yes no)
733
734 // Disabled because it interferes with the pattern match above and makes worse code.
735 // (SETNEF x) => (ORQ (SETNE <typ.Int8> x) (SETNAN <typ.Int8> x))
736 // (SETEQF x) => (ANDQ (SETEQ <typ.Int8> x) (SETORD <typ.Int8> x))
737
738 // fold constants into instructions
739 (ADDQ x (MOVQconst <t> [c])) && is32Bit(c) && !t.IsPtr() => (ADDQconst [int32(c)] x)
740 (ADDQ x (MOVLconst [c])) => (ADDQconst [c] x)
741 (ADDL x (MOVLconst [c])) => (ADDLconst [c] x)
742
743 (SUBQ x (MOVQconst [c])) && is32Bit(c) => (SUBQconst x [int32(c)])
744 (SUBQ (MOVQconst [c]) x) && is32Bit(c) => (NEGQ (SUBQconst <v.Type> x [int32(c)]))
745 (SUBL x (MOVLconst [c])) => (SUBLconst x [c])
746 (SUBL (MOVLconst [c]) x) => (NEGL (SUBLconst <v.Type> x [c]))
747
748 (MULQ x (MOVQconst [c])) && is32Bit(c) => (MULQconst [int32(c)] x)
749 (MULL x (MOVLconst [c])) => (MULLconst [c] x)
750
751 (ANDQ x (MOVQconst [c])) && is32Bit(c) => (ANDQconst [int32(c)] x)
752 (ANDL x (MOVLconst [c])) => (ANDLconst [c] x)
753
754 (AND(L|Q)const [c] (AND(L|Q)const [d] x)) => (AND(L|Q)const [c & d] x)
755 (XOR(L|Q)const [c] (XOR(L|Q)const [d] x)) => (XOR(L|Q)const [c ^ d] x)
756 (OR(L|Q)const [c] (OR(L|Q)const [d] x)) => (OR(L|Q)const [c | d] x)
757
758 (MULLconst [c] (MULLconst [d] x)) => (MULLconst [c * d] x)
759 (MULQconst [c] (MULQconst [d] x)) && is32Bit(int64(c)*int64(d)) => (MULQconst [c * d] x)
760
761 (ORQ x (MOVQconst [c])) && is32Bit(c) => (ORQconst [int32(c)] x)
762 (ORQ x (MOVLconst [c])) => (ORQconst [c] x)
763 (ORL x (MOVLconst [c])) => (ORLconst [c] x)
764
765 (XORQ x (MOVQconst [c])) && is32Bit(c) => (XORQconst [int32(c)] x)
766 (XORL x (MOVLconst [c])) => (XORLconst [c] x)
767
768 (SHLQ x (MOV(Q|L)const [c])) => (SHLQconst [int8(c&63)] x)
769 (SHLL x (MOV(Q|L)const [c])) => (SHLLconst [int8(c&31)] x)
770
771 (SHRQ x (MOV(Q|L)const [c])) => (SHRQconst [int8(c&63)] x)
772 (SHRL x (MOV(Q|L)const [c])) => (SHRLconst [int8(c&31)] x)
773 (SHRW x (MOV(Q|L)const [c])) && c&31 < 16 => (SHRWconst [int8(c&31)] x)
774 (SHRW _ (MOV(Q|L)const [c])) && c&31 >= 16 => (MOVLconst [0])
775 (SHRB x (MOV(Q|L)const [c])) && c&31 < 8 => (SHRBconst [int8(c&31)] x)
776 (SHRB _ (MOV(Q|L)const [c])) && c&31 >= 8 => (MOVLconst [0])
777
778 (SARQ x (MOV(Q|L)const [c])) => (SARQconst [int8(c&63)] x)
779 (SARL x (MOV(Q|L)const [c])) => (SARLconst [int8(c&31)] x)
780 (SARW x (MOV(Q|L)const [c])) => (SARWconst [int8(min(int64(c)&31,15))] x)
781 (SARB x (MOV(Q|L)const [c])) => (SARBconst [int8(min(int64(c)&31,7))] x)
782
783 // Operations which don't affect the low 6/5 bits of the shift amount are NOPs.
784 ((SHLQ|SHRQ|SARQ) x (ADDQconst [c] y)) && c & 63 == 0 => ((SHLQ|SHRQ|SARQ) x y)
785 ((SHLQ|SHRQ|SARQ) x (NEGQ <t> (ADDQconst [c] y))) && c & 63 == 0 => ((SHLQ|SHRQ|SARQ) x (NEGQ <t> y))
786 ((SHLQ|SHRQ|SARQ) x (ANDQconst [c] y)) && c & 63 == 63 => ((SHLQ|SHRQ|SARQ) x y)
787 ((SHLQ|SHRQ|SARQ) x (NEGQ <t> (ANDQconst [c] y))) && c & 63 == 63 => ((SHLQ|SHRQ|SARQ) x (NEGQ <t> y))
788
789 ((SHLL|SHRL|SARL) x (ADDQconst [c] y)) && c & 31 == 0 => ((SHLL|SHRL|SARL) x y)
790 ((SHLL|SHRL|SARL) x (NEGQ <t> (ADDQconst [c] y))) && c & 31 == 0 => ((SHLL|SHRL|SARL) x (NEGQ <t> y))
791 ((SHLL|SHRL|SARL) x (ANDQconst [c] y)) && c & 31 == 31 => ((SHLL|SHRL|SARL) x y)
792 ((SHLL|SHRL|SARL) x (NEGQ <t> (ANDQconst [c] y))) && c & 31 == 31 => ((SHLL|SHRL|SARL) x (NEGQ <t> y))
793
794 ((SHLQ|SHRQ|SARQ) x (ADDLconst [c] y)) && c & 63 == 0 => ((SHLQ|SHRQ|SARQ) x y)
795 ((SHLQ|SHRQ|SARQ) x (NEGL <t> (ADDLconst [c] y))) && c & 63 == 0 => ((SHLQ|SHRQ|SARQ) x (NEGL <t> y))
796 ((SHLQ|SHRQ|SARQ) x (ANDLconst [c] y)) && c & 63 == 63 => ((SHLQ|SHRQ|SARQ) x y)
797 ((SHLQ|SHRQ|SARQ) x (NEGL <t> (ANDLconst [c] y))) && c & 63 == 63 => ((SHLQ|SHRQ|SARQ) x (NEGL <t> y))
798
799 ((SHLL|SHRL|SARL) x (ADDLconst [c] y)) && c & 31 == 0 => ((SHLL|SHRL|SARL) x y)
800 ((SHLL|SHRL|SARL) x (NEGL <t> (ADDLconst [c] y))) && c & 31 == 0 => ((SHLL|SHRL|SARL) x (NEGL <t> y))
801 ((SHLL|SHRL|SARL) x (ANDLconst [c] y)) && c & 31 == 31 => ((SHLL|SHRL|SARL) x y)
802 ((SHLL|SHRL|SARL) x (NEGL <t> (ANDLconst [c] y))) && c & 31 == 31 => ((SHLL|SHRL|SARL) x (NEGL <t> y))
803
804 // rotate left negative = rotate right
805 (ROLQ x (NEG(Q|L) y)) => (RORQ x y)
806 (ROLL x (NEG(Q|L) y)) => (RORL x y)
807 (ROLW x (NEG(Q|L) y)) => (RORW x y)
808 (ROLB x (NEG(Q|L) y)) => (RORB x y)
809
810 // rotate right negative = rotate left
811 (RORQ x (NEG(Q|L) y)) => (ROLQ x y)
812 (RORL x (NEG(Q|L) y)) => (ROLL x y)
813 (RORW x (NEG(Q|L) y)) => (ROLW x y)
814 (RORB x (NEG(Q|L) y)) => (ROLB x y)
815
816 // rotate by constants
817 (ROLQ x (MOV(Q|L)const [c])) => (ROLQconst [int8(c&63)] x)
818 (ROLL x (MOV(Q|L)const [c])) => (ROLLconst [int8(c&31)] x)
819 (ROLW x (MOV(Q|L)const [c])) => (ROLWconst [int8(c&15)] x)
820 (ROLB x (MOV(Q|L)const [c])) => (ROLBconst [int8(c&7) ] x)
821
822 (RORQ x (MOV(Q|L)const [c])) => (ROLQconst [int8((-c)&63)] x)
823 (RORL x (MOV(Q|L)const [c])) => (ROLLconst [int8((-c)&31)] x)
824 (RORW x (MOV(Q|L)const [c])) => (ROLWconst [int8((-c)&15)] x)
825 (RORB x (MOV(Q|L)const [c])) => (ROLBconst [int8((-c)&7) ] x)
826
827 // Constant shift simplifications
828 ((SHLQ|SHRQ|SARQ)const x [0]) => x
829 ((SHLL|SHRL|SARL)const x [0]) => x
830 ((SHRW|SARW)const x [0]) => x
831 ((SHRB|SARB)const x [0]) => x
832 ((ROLQ|ROLL|ROLW|ROLB)const x [0]) => x
833
834 // Note: the word and byte shifts keep the low 5 bits (not the low 4 or 3 bits)
835 // because the x86 instructions are defined to use all 5 bits of the shift even
836 // for the small shifts. I don't think we'll ever generate a weird shift (e.g.
837 // (SHRW x (MOVLconst [24])), but just in case.
838
839 (CMPQ x (MOVQconst [c])) && is32Bit(c) => (CMPQconst x [int32(c)])
840 (CMPQ (MOVQconst [c]) x) && is32Bit(c) => (InvertFlags (CMPQconst x [int32(c)]))
841 (CMPL x (MOVLconst [c])) => (CMPLconst x [c])
842 (CMPL (MOVLconst [c]) x) => (InvertFlags (CMPLconst x [c]))
843 (CMPW x (MOVLconst [c])) => (CMPWconst x [int16(c)])
844 (CMPW (MOVLconst [c]) x) => (InvertFlags (CMPWconst x [int16(c)]))
845 (CMPB x (MOVLconst [c])) => (CMPBconst x [int8(c)])
846 (CMPB (MOVLconst [c]) x) => (InvertFlags (CMPBconst x [int8(c)]))
847
848 // Canonicalize the order of arguments to comparisons - helps with CSE.
849 (CMP(Q|L|W|B) x y) && canonLessThan(x,y) => (InvertFlags (CMP(Q|L|W|B) y x))
850
851 // Using MOVZX instead of AND is cheaper.
852 (AND(Q|L)const [ 0xFF] x) => (MOVBQZX x)
853 (AND(Q|L)const [0xFFFF] x) => (MOVWQZX x)
854 // This rule is currently invalid because 0xFFFFFFFF is not representable by a signed int32.
855 // Commenting out for now, because it also can't trigger because of the is32bit guard on the
856 // ANDQconst lowering-rule, above, prevents 0xFFFFFFFF from matching (for the same reason)
857 // Using an alternate form of this rule segfaults some binaries because of
858 // adverse interactions with other passes.
859 // (ANDQconst [0xFFFFFFFF] x) => (MOVLQZX x)
860
861 // strength reduction
862 (MUL(Q|L)const [ 0] _) => (MOV(Q|L)const [0])
863 (MUL(Q|L)const [ 1] x) => x
864 (MULQconst [c] x) && canMulStrengthReduce(config, int64(c)) => {mulStrengthReduce(v, x, int64(c))}
865 (MULLconst [c] x) && v.Type.Size() <= 4 && canMulStrengthReduce32(config, c) => {mulStrengthReduce32(v, x, c)}
866
867 // Prefer addition when shifting left by one
868 (SHL(Q|L)const [1] x) => (ADD(Q|L) x x)
869
870 // combine add/shift into LEAQ/LEAL
871 (ADD(L|Q) x (SHL(L|Q)const [3] y)) => (LEA(L|Q)8 x y)
872 (ADD(L|Q) x (SHL(L|Q)const [2] y)) => (LEA(L|Q)4 x y)
873 (ADD(L|Q) x (ADD(L|Q) y y)) => (LEA(L|Q)2 x y)
874 (ADD(L|Q) x (ADD(L|Q) x y)) => (LEA(L|Q)2 y x)
875
876 // combine ADDQ/ADDQconst into LEAQ1/LEAL1
877 (ADD(Q|L)const [c] (ADD(Q|L) x y)) => (LEA(Q|L)1 [c] x y)
878 (ADD(Q|L) (ADD(Q|L)const [c] x) y) => (LEA(Q|L)1 [c] x y)
879 (ADD(Q|L)const [c] (ADD(Q|L) x x)) => (LEA(Q|L)1 [c] x x)
880
881 // fold ADDQ/ADDL into LEAQ/LEAL
882 (ADD(Q|L)const [c] (LEA(Q|L) [d] {s} x)) && is32Bit(int64(c)+int64(d)) => (LEA(Q|L) [c+d] {s} x)
883 (LEA(Q|L) [c] {s} (ADD(Q|L)const [d] x)) && is32Bit(int64(c)+int64(d)) => (LEA(Q|L) [c+d] {s} x)
884 (LEA(Q|L) [c] {s} (ADD(Q|L) x y)) && x.Op != OpSB && y.Op != OpSB => (LEA(Q|L)1 [c] {s} x y)
885 (ADD(Q|L) x (LEA(Q|L) [c] {s} y)) && x.Op != OpSB && y.Op != OpSB => (LEA(Q|L)1 [c] {s} x y)
886
887 // fold ADDQconst/ADDLconst into LEAQx/LEALx
888 (ADD(Q|L)const [c] (LEA(Q|L)1 [d] {s} x y)) && is32Bit(int64(c)+int64(d)) => (LEA(Q|L)1 [c+d] {s} x y)
889 (ADD(Q|L)const [c] (LEA(Q|L)2 [d] {s} x y)) && is32Bit(int64(c)+int64(d)) => (LEA(Q|L)2 [c+d] {s} x y)
890 (ADD(Q|L)const [c] (LEA(Q|L)4 [d] {s} x y)) && is32Bit(int64(c)+int64(d)) => (LEA(Q|L)4 [c+d] {s} x y)
891 (ADD(Q|L)const [c] (LEA(Q|L)8 [d] {s} x y)) && is32Bit(int64(c)+int64(d)) => (LEA(Q|L)8 [c+d] {s} x y)
892 (LEA(Q|L)1 [c] {s} (ADD(Q|L)const [d] x) y) && is32Bit(int64(c)+int64(d)) && x.Op != OpSB => (LEA(Q|L)1 [c+d] {s} x y)
893 (LEA(Q|L)2 [c] {s} (ADD(Q|L)const [d] x) y) && is32Bit(int64(c)+int64(d)) && x.Op != OpSB => (LEA(Q|L)2 [c+d] {s} x y)
894 (LEA(Q|L)2 [c] {s} x (ADD(Q|L)const [d] y)) && is32Bit(int64(c)+2*int64(d)) && y.Op != OpSB => (LEA(Q|L)2 [c+2*d] {s} x y)
895 (LEA(Q|L)4 [c] {s} (ADD(Q|L)const [d] x) y) && is32Bit(int64(c)+int64(d)) && x.Op != OpSB => (LEA(Q|L)4 [c+d] {s} x y)
896 (LEA(Q|L)4 [c] {s} x (ADD(Q|L)const [d] y)) && is32Bit(int64(c)+4*int64(d)) && y.Op != OpSB => (LEA(Q|L)4 [c+4*d] {s} x y)
897 (LEA(Q|L)8 [c] {s} (ADD(Q|L)const [d] x) y) && is32Bit(int64(c)+int64(d)) && x.Op != OpSB => (LEA(Q|L)8 [c+d] {s} x y)
898 (LEA(Q|L)8 [c] {s} x (ADD(Q|L)const [d] y)) && is32Bit(int64(c)+8*int64(d)) && y.Op != OpSB => (LEA(Q|L)8 [c+8*d] {s} x y)
899
900 // fold shifts into LEAQx/LEALx
901 (LEA(Q|L)1 [c] {s} x z:(ADD(Q|L) y y)) && x != z => (LEA(Q|L)2 [c] {s} x y)
902 (LEA(Q|L)1 [c] {s} x (SHL(Q|L)const [2] y)) => (LEA(Q|L)4 [c] {s} x y)
903 (LEA(Q|L)1 [c] {s} x (SHL(Q|L)const [3] y)) => (LEA(Q|L)8 [c] {s} x y)
904 (LEA(Q|L)2 [c] {s} x z:(ADD(Q|L) y y)) && x != z => (LEA(Q|L)4 [c] {s} x y)
905 (LEA(Q|L)2 [c] {s} x (SHL(Q|L)const [2] y)) => (LEA(Q|L)8 [c] {s} x y)
906 (LEA(Q|L)4 [c] {s} x z:(ADD(Q|L) y y)) && x != z => (LEA(Q|L)8 [c] {s} x y)
907
908 // (x + x) << 1 -> x << 2
909 (LEA(Q|L)2 [0] {s} (ADD(Q|L) x x) x) && s == nil => (SHL(Q|L)const [2] x)
910
911 // (x + x) << 2 -> x << 3 and similar
912 (SHLQconst [c] (ADDQ x x)) && c < 63 => (SHLQconst [c+1] x)
913 (SHLLconst [c] (ADDL x x)) && c < 31 => (SHLLconst [c+1] x)
914
915 // reverse ordering of compare instruction
916 (SETL (InvertFlags x)) => (SETG x)
917 (SETG (InvertFlags x)) => (SETL x)
918 (SETB (InvertFlags x)) => (SETA x)
919 (SETA (InvertFlags x)) => (SETB x)
920 (SETLE (InvertFlags x)) => (SETGE x)
921 (SETGE (InvertFlags x)) => (SETLE x)
922 (SETBE (InvertFlags x)) => (SETAE x)
923 (SETAE (InvertFlags x)) => (SETBE x)
924 (SETEQ (InvertFlags x)) => (SETEQ x)
925 (SETNE (InvertFlags x)) => (SETNE x)
926
927 (SETLstore [off] {sym} ptr (InvertFlags x) mem) => (SETGstore [off] {sym} ptr x mem)
928 (SETGstore [off] {sym} ptr (InvertFlags x) mem) => (SETLstore [off] {sym} ptr x mem)
929 (SETBstore [off] {sym} ptr (InvertFlags x) mem) => (SETAstore [off] {sym} ptr x mem)
930 (SETAstore [off] {sym} ptr (InvertFlags x) mem) => (SETBstore [off] {sym} ptr x mem)
931 (SETLEstore [off] {sym} ptr (InvertFlags x) mem) => (SETGEstore [off] {sym} ptr x mem)
932 (SETGEstore [off] {sym} ptr (InvertFlags x) mem) => (SETLEstore [off] {sym} ptr x mem)
933 (SETBEstore [off] {sym} ptr (InvertFlags x) mem) => (SETAEstore [off] {sym} ptr x mem)
934 (SETAEstore [off] {sym} ptr (InvertFlags x) mem) => (SETBEstore [off] {sym} ptr x mem)
935 (SETEQstore [off] {sym} ptr (InvertFlags x) mem) => (SETEQstore [off] {sym} ptr x mem)
936 (SETNEstore [off] {sym} ptr (InvertFlags x) mem) => (SETNEstore [off] {sym} ptr x mem)
937
938 // sign extended loads
939 // Note: The combined instruction must end up in the same block
940 // as the original load. If not, we end up making a value with
941 // memory type live in two different blocks, which can lead to
942 // multiple memory values alive simultaneously.
943 // Make sure we don't combine these ops if the load has another use.
944 // This prevents a single load from being split into multiple loads
945 // which then might return different values. See test/atomicload.go.
946 (MOVBQSX x:(MOVBload [off] {sym} ptr mem)) && x.Uses == 1 && clobber(x) => @x.Block (MOVBQSXload <v.Type> [off] {sym} ptr mem)
947 (MOVBQSX x:(MOVWload [off] {sym} ptr mem)) && x.Uses == 1 && clobber(x) => @x.Block (MOVBQSXload <v.Type> [off] {sym} ptr mem)
948 (MOVBQSX x:(MOVLload [off] {sym} ptr mem)) && x.Uses == 1 && clobber(x) => @x.Block (MOVBQSXload <v.Type> [off] {sym} ptr mem)
949 (MOVBQSX x:(MOVQload [off] {sym} ptr mem)) && x.Uses == 1 && clobber(x) => @x.Block (MOVBQSXload <v.Type> [off] {sym} ptr mem)
950 (MOVBQZX x:(MOVBload [off] {sym} ptr mem)) && x.Uses == 1 && clobber(x) => @x.Block (MOVBload <v.Type> [off] {sym} ptr mem)
951 (MOVBQZX x:(MOVWload [off] {sym} ptr mem)) && x.Uses == 1 && clobber(x) => @x.Block (MOVBload <v.Type> [off] {sym} ptr mem)
952 (MOVBQZX x:(MOVLload [off] {sym} ptr mem)) && x.Uses == 1 && clobber(x) => @x.Block (MOVBload <v.Type> [off] {sym} ptr mem)
953 (MOVBQZX x:(MOVQload [off] {sym} ptr mem)) && x.Uses == 1 && clobber(x) => @x.Block (MOVBload <v.Type> [off] {sym} ptr mem)
954 (MOVWQSX x:(MOVWload [off] {sym} ptr mem)) && x.Uses == 1 && clobber(x) => @x.Block (MOVWQSXload <v.Type> [off] {sym} ptr mem)
955 (MOVWQSX x:(MOVLload [off] {sym} ptr mem)) && x.Uses == 1 && clobber(x) => @x.Block (MOVWQSXload <v.Type> [off] {sym} ptr mem)
956 (MOVWQSX x:(MOVQload [off] {sym} ptr mem)) && x.Uses == 1 && clobber(x) => @x.Block (MOVWQSXload <v.Type> [off] {sym} ptr mem)
957 (MOVWQZX x:(MOVWload [off] {sym} ptr mem)) && x.Uses == 1 && clobber(x) => @x.Block (MOVWload <v.Type> [off] {sym} ptr mem)
958 (MOVWQZX x:(MOVLload [off] {sym} ptr mem)) && x.Uses == 1 && clobber(x) => @x.Block (MOVWload <v.Type> [off] {sym} ptr mem)
959 (MOVWQZX x:(MOVQload [off] {sym} ptr mem)) && x.Uses == 1 && clobber(x) => @x.Block (MOVWload <v.Type> [off] {sym} ptr mem)
960 (MOVLQSX x:(MOVLload [off] {sym} ptr mem)) && x.Uses == 1 && clobber(x) => @x.Block (MOVLQSXload <v.Type> [off] {sym} ptr mem)
961 (MOVLQSX x:(MOVQload [off] {sym} ptr mem)) && x.Uses == 1 && clobber(x) => @x.Block (MOVLQSXload <v.Type> [off] {sym} ptr mem)
962 (MOVLQZX x:(MOVLload [off] {sym} ptr mem)) && x.Uses == 1 && clobber(x) => @x.Block (MOVLload <v.Type> [off] {sym} ptr mem)
963 (MOVLQZX x:(MOVQload [off] {sym} ptr mem)) && x.Uses == 1 && clobber(x) => @x.Block (MOVLload <v.Type> [off] {sym} ptr mem)
964
965 // replace load from same location as preceding store with zero/sign extension (or copy in case of full width)
966 (MOVBload [off] {sym} ptr (MOVBstore [off2] {sym2} ptr2 x _)) && sym == sym2 && off == off2 && isSamePtr(ptr, ptr2) => (MOVBQZX x)
967 (MOVWload [off] {sym} ptr (MOVWstore [off2] {sym2} ptr2 x _)) && sym == sym2 && off == off2 && isSamePtr(ptr, ptr2) => (MOVWQZX x)
968 (MOVLload [off] {sym} ptr (MOVLstore [off2] {sym2} ptr2 x _)) && sym == sym2 && off == off2 && isSamePtr(ptr, ptr2) => (MOVLQZX x)
969 (MOVQload [off] {sym} ptr (MOVQstore [off2] {sym2} ptr2 x _)) && sym == sym2 && off == off2 && isSamePtr(ptr, ptr2) => x
970 (MOVBQSXload [off] {sym} ptr (MOVBstore [off2] {sym2} ptr2 x _)) && sym == sym2 && off == off2 && isSamePtr(ptr, ptr2) => (MOVBQSX x)
971 (MOVWQSXload [off] {sym} ptr (MOVWstore [off2] {sym2} ptr2 x _)) && sym == sym2 && off == off2 && isSamePtr(ptr, ptr2) => (MOVWQSX x)
972 (MOVLQSXload [off] {sym} ptr (MOVLstore [off2] {sym2} ptr2 x _)) && sym == sym2 && off == off2 && isSamePtr(ptr, ptr2) => (MOVLQSX x)
973
974 // Fold extensions and ANDs together.
975 (MOVBQZX (ANDLconst [c] x)) => (ANDLconst [c & 0xff] x)
976 (MOVWQZX (ANDLconst [c] x)) => (ANDLconst [c & 0xffff] x)
977 (MOVLQZX (ANDLconst [c] x)) => (ANDLconst [c] x)
978 (MOVBQSX (ANDLconst [c] x)) && c & 0x80 == 0 => (ANDLconst [c & 0x7f] x)
979 (MOVWQSX (ANDLconst [c] x)) && c & 0x8000 == 0 => (ANDLconst [c & 0x7fff] x)
980 (MOVLQSX (ANDLconst [c] x)) && uint32(c) & 0x80000000 == 0 => (ANDLconst [c & 0x7fffffff] x)
981
982 // Don't extend before storing
983 (MOVLstore [off] {sym} ptr (MOVLQSX x) mem) => (MOVLstore [off] {sym} ptr x mem)
984 (MOVWstore [off] {sym} ptr (MOVWQSX x) mem) => (MOVWstore [off] {sym} ptr x mem)
985 (MOVBstore [off] {sym} ptr (MOVBQSX x) mem) => (MOVBstore [off] {sym} ptr x mem)
986 (MOVLstore [off] {sym} ptr (MOVLQZX x) mem) => (MOVLstore [off] {sym} ptr x mem)
987 (MOVWstore [off] {sym} ptr (MOVWQZX x) mem) => (MOVWstore [off] {sym} ptr x mem)
988 (MOVBstore [off] {sym} ptr (MOVBQZX x) mem) => (MOVBstore [off] {sym} ptr x mem)
989
990 // fold constants into memory operations
991 // Note that this is not always a good idea because if not all the uses of
992 // the ADDQconst get eliminated, we still have to compute the ADDQconst and we now
993 // have potentially two live values (ptr and (ADDQconst [off] ptr)) instead of one.
994 // Nevertheless, let's do it!
995 (MOV(Q|L|W|B|SS|SD|O)load [off1] {sym} (ADDQconst [off2] ptr) mem) && is32Bit(int64(off1)+int64(off2)) =>
996 (MOV(Q|L|W|B|SS|SD|O)load [off1+off2] {sym} ptr mem)
997 (MOV(Q|L|W|B|SS|SD|O)store [off1] {sym} (ADDQconst [off2] ptr) val mem) && is32Bit(int64(off1)+int64(off2)) =>
998 (MOV(Q|L|W|B|SS|SD|O)store [off1+off2] {sym} ptr val mem)
999 (SET(L|G|B|A|LE|GE|BE|AE|EQ|NE)store [off1] {sym} (ADDQconst [off2] base) val mem) && is32Bit(int64(off1)+int64(off2)) =>
1000 (SET(L|G|B|A|LE|GE|BE|AE|EQ|NE)store [off1+off2] {sym} base val mem)
1001 ((ADD|SUB|AND|OR|XOR)Qload [off1] {sym} val (ADDQconst [off2] base) mem) && is32Bit(int64(off1)+int64(off2)) =>
1002 ((ADD|SUB|AND|OR|XOR)Qload [off1+off2] {sym} val base mem)
1003 ((ADD|SUB|AND|OR|XOR)Lload [off1] {sym} val (ADDQconst [off2] base) mem) && is32Bit(int64(off1)+int64(off2)) =>
1004 ((ADD|SUB|AND|OR|XOR)Lload [off1+off2] {sym} val base mem)
1005 (CMP(Q|L|W|B)load [off1] {sym} (ADDQconst [off2] base) val mem) && is32Bit(int64(off1)+int64(off2)) =>
1006 (CMP(Q|L|W|B)load [off1+off2] {sym} base val mem)
1007 (CMP(Q|L|W|B)constload [valoff1] {sym} (ADDQconst [off2] base) mem) && ValAndOff(valoff1).canAdd32(off2) =>
1008 (CMP(Q|L|W|B)constload [ValAndOff(valoff1).addOffset32(off2)] {sym} base mem)
1009
1010 ((ADD|SUB|MUL|DIV)SSload [off1] {sym} val (ADDQconst [off2] base) mem) && is32Bit(int64(off1)+int64(off2)) =>
1011 ((ADD|SUB|MUL|DIV)SSload [off1+off2] {sym} val base mem)
1012 ((ADD|SUB|MUL|DIV)SDload [off1] {sym} val (ADDQconst [off2] base) mem) && is32Bit(int64(off1)+int64(off2)) =>
1013 ((ADD|SUB|MUL|DIV)SDload [off1+off2] {sym} val base mem)
1014 ((ADD|AND|OR|XOR)Qconstmodify [valoff1] {sym} (ADDQconst [off2] base) mem) && ValAndOff(valoff1).canAdd32(off2) =>
1015 ((ADD|AND|OR|XOR)Qconstmodify [ValAndOff(valoff1).addOffset32(off2)] {sym} base mem)
1016 ((ADD|AND|OR|XOR)Lconstmodify [valoff1] {sym} (ADDQconst [off2] base) mem) && ValAndOff(valoff1).canAdd32(off2) =>
1017 ((ADD|AND|OR|XOR)Lconstmodify [ValAndOff(valoff1).addOffset32(off2)] {sym} base mem)
1018 ((ADD|SUB|AND|OR|XOR)Qmodify [off1] {sym} (ADDQconst [off2] base) val mem) && is32Bit(int64(off1)+int64(off2)) =>
1019 ((ADD|SUB|AND|OR|XOR)Qmodify [off1+off2] {sym} base val mem)
1020 ((ADD|SUB|AND|OR|XOR)Lmodify [off1] {sym} (ADDQconst [off2] base) val mem) && is32Bit(int64(off1)+int64(off2)) =>
1021 ((ADD|SUB|AND|OR|XOR)Lmodify [off1+off2] {sym} base val mem)
1022
1023 // Fold constants into stores.
1024 (MOVQstore [off] {sym} ptr (MOVQconst [c]) mem) && validVal(c) =>
1025 (MOVQstoreconst [makeValAndOff(int32(c),off)] {sym} ptr mem)
1026 (MOVLstore [off] {sym} ptr (MOV(L|Q)const [c]) mem) =>
1027 (MOVLstoreconst [makeValAndOff(int32(c),off)] {sym} ptr mem)
1028 (MOVWstore [off] {sym} ptr (MOV(L|Q)const [c]) mem) =>
1029 (MOVWstoreconst [makeValAndOff(int32(int16(c)),off)] {sym} ptr mem)
1030 (MOVBstore [off] {sym} ptr (MOV(L|Q)const [c]) mem) =>
1031 (MOVBstoreconst [makeValAndOff(int32(int8(c)),off)] {sym} ptr mem)
1032
1033 // Fold address offsets into constant stores.
1034 (MOV(Q|L|W|B|O)storeconst [sc] {s} (ADDQconst [off] ptr) mem) && ValAndOff(sc).canAdd32(off) =>
1035 (MOV(Q|L|W|B|O)storeconst [ValAndOff(sc).addOffset32(off)] {s} ptr mem)
1036
1037 // We need to fold LEAQ into the MOVx ops so that the live variable analysis knows
1038 // what variables are being read/written by the ops.
1039 (MOV(Q|L|W|B|SS|SD|O|BQSX|WQSX|LQSX)load [off1] {sym1} (LEAQ [off2] {sym2} base) mem)
1040 && is32Bit(int64(off1)+int64(off2)) && canMergeSym(sym1, sym2) =>
1041 (MOV(Q|L|W|B|SS|SD|O|BQSX|WQSX|LQSX)load [off1+off2] {mergeSym(sym1,sym2)} base mem)
1042 (MOV(Q|L|W|B|SS|SD|O)store [off1] {sym1} (LEAQ [off2] {sym2} base) val mem)
1043 && is32Bit(int64(off1)+int64(off2)) && canMergeSym(sym1, sym2) =>
1044 (MOV(Q|L|W|B|SS|SD|O)store [off1+off2] {mergeSym(sym1,sym2)} base val mem)
1045 (MOV(Q|L|W|B|O)storeconst [sc] {sym1} (LEAQ [off] {sym2} ptr) mem) && canMergeSym(sym1, sym2) && ValAndOff(sc).canAdd32(off) =>
1046 (MOV(Q|L|W|B|O)storeconst [ValAndOff(sc).addOffset32(off)] {mergeSym(sym1, sym2)} ptr mem)
1047 (SET(L|G|B|A|LE|GE|BE|AE|EQ|NE)store [off1] {sym1} (LEAQ [off2] {sym2} base) val mem)
1048 && is32Bit(int64(off1)+int64(off2)) && canMergeSym(sym1, sym2) =>
1049 (SET(L|G|B|A|LE|GE|BE|AE|EQ|NE)store [off1+off2] {mergeSym(sym1,sym2)} base val mem)
1050 ((ADD|SUB|AND|OR|XOR)Qload [off1] {sym1} val (LEAQ [off2] {sym2} base) mem)
1051 && is32Bit(int64(off1)+int64(off2)) && canMergeSym(sym1, sym2) =>
1052 ((ADD|SUB|AND|OR|XOR)Qload [off1+off2] {mergeSym(sym1,sym2)} val base mem)
1053 ((ADD|SUB|AND|OR|XOR)Lload [off1] {sym1} val (LEAQ [off2] {sym2} base) mem)
1054 && is32Bit(int64(off1)+int64(off2)) && canMergeSym(sym1, sym2) =>
1055 ((ADD|SUB|AND|OR|XOR)Lload [off1+off2] {mergeSym(sym1,sym2)} val base mem)
1056 (CMP(Q|L|W|B)load [off1] {sym1} (LEAQ [off2] {sym2} base) val mem)
1057 && is32Bit(int64(off1)+int64(off2)) && canMergeSym(sym1, sym2) =>
1058 (CMP(Q|L|W|B)load [off1+off2] {mergeSym(sym1,sym2)} base val mem)
1059 (CMP(Q|L|W|B)constload [valoff1] {sym1} (LEAQ [off2] {sym2} base) mem)
1060 && ValAndOff(valoff1).canAdd32(off2) && canMergeSym(sym1, sym2) =>
1061 (CMP(Q|L|W|B)constload [ValAndOff(valoff1).addOffset32(off2)] {mergeSym(sym1,sym2)} base mem)
1062
1063 ((ADD|SUB|MUL|DIV)SSload [off1] {sym1} val (LEAQ [off2] {sym2} base) mem)
1064 && is32Bit(int64(off1)+int64(off2)) && canMergeSym(sym1, sym2) =>
1065 ((ADD|SUB|MUL|DIV)SSload [off1+off2] {mergeSym(sym1,sym2)} val base mem)
1066 ((ADD|SUB|MUL|DIV)SDload [off1] {sym1} val (LEAQ [off2] {sym2} base) mem)
1067 && is32Bit(int64(off1)+int64(off2)) && canMergeSym(sym1, sym2) =>
1068 ((ADD|SUB|MUL|DIV)SDload [off1+off2] {mergeSym(sym1,sym2)} val base mem)
1069 ((ADD|AND|OR|XOR)Qconstmodify [valoff1] {sym1} (LEAQ [off2] {sym2} base) mem)
1070 && ValAndOff(valoff1).canAdd32(off2) && canMergeSym(sym1, sym2) =>
1071 ((ADD|AND|OR|XOR)Qconstmodify [ValAndOff(valoff1).addOffset32(off2)] {mergeSym(sym1,sym2)} base mem)
1072 ((ADD|AND|OR|XOR)Lconstmodify [valoff1] {sym1} (LEAQ [off2] {sym2} base) mem)
1073 && ValAndOff(valoff1).canAdd32(off2) && canMergeSym(sym1, sym2) =>
1074 ((ADD|AND|OR|XOR)Lconstmodify [ValAndOff(valoff1).addOffset32(off2)] {mergeSym(sym1,sym2)} base mem)
1075 ((ADD|SUB|AND|OR|XOR)Qmodify [off1] {sym1} (LEAQ [off2] {sym2} base) val mem)
1076 && is32Bit(int64(off1)+int64(off2)) && canMergeSym(sym1, sym2) =>
1077 ((ADD|SUB|AND|OR|XOR)Qmodify [off1+off2] {mergeSym(sym1,sym2)} base val mem)
1078 ((ADD|SUB|AND|OR|XOR)Lmodify [off1] {sym1} (LEAQ [off2] {sym2} base) val mem)
1079 && is32Bit(int64(off1)+int64(off2)) && canMergeSym(sym1, sym2) =>
1080 ((ADD|SUB|AND|OR|XOR)Lmodify [off1+off2] {mergeSym(sym1,sym2)} base val mem)
1081
1082 // fold LEAQs together
1083 (LEAQ [off1] {sym1} (LEAQ [off2] {sym2} x)) && is32Bit(int64(off1)+int64(off2)) && canMergeSym(sym1, sym2) =>
1084 (LEAQ [off1+off2] {mergeSym(sym1,sym2)} x)
1085
1086 // LEAQ into LEAQ1
1087 (LEAQ1 [off1] {sym1} (LEAQ [off2] {sym2} x) y) && is32Bit(int64(off1)+int64(off2)) && canMergeSym(sym1, sym2) && x.Op != OpSB =>
1088 (LEAQ1 [off1+off2] {mergeSym(sym1,sym2)} x y)
1089
1090 // LEAQ1 into LEAQ
1091 (LEAQ [off1] {sym1} (LEAQ1 [off2] {sym2} x y)) && is32Bit(int64(off1)+int64(off2)) && canMergeSym(sym1, sym2) =>
1092 (LEAQ1 [off1+off2] {mergeSym(sym1,sym2)} x y)
1093
1094 // LEAQ into LEAQ[248]
1095 (LEAQ2 [off1] {sym1} (LEAQ [off2] {sym2} x) y) && is32Bit(int64(off1)+int64(off2)) && canMergeSym(sym1, sym2) && x.Op != OpSB =>
1096 (LEAQ2 [off1+off2] {mergeSym(sym1,sym2)} x y)
1097 (LEAQ4 [off1] {sym1} (LEAQ [off2] {sym2} x) y) && is32Bit(int64(off1)+int64(off2)) && canMergeSym(sym1, sym2) && x.Op != OpSB =>
1098 (LEAQ4 [off1+off2] {mergeSym(sym1,sym2)} x y)
1099 (LEAQ8 [off1] {sym1} (LEAQ [off2] {sym2} x) y) && is32Bit(int64(off1)+int64(off2)) && canMergeSym(sym1, sym2) && x.Op != OpSB =>
1100 (LEAQ8 [off1+off2] {mergeSym(sym1,sym2)} x y)
1101
1102 // LEAQ[248] into LEAQ
1103 (LEAQ [off1] {sym1} (LEAQ2 [off2] {sym2} x y)) && is32Bit(int64(off1)+int64(off2)) && canMergeSym(sym1, sym2) =>
1104 (LEAQ2 [off1+off2] {mergeSym(sym1,sym2)} x y)
1105 (LEAQ [off1] {sym1} (LEAQ4 [off2] {sym2} x y)) && is32Bit(int64(off1)+int64(off2)) && canMergeSym(sym1, sym2) =>
1106 (LEAQ4 [off1+off2] {mergeSym(sym1,sym2)} x y)
1107 (LEAQ [off1] {sym1} (LEAQ8 [off2] {sym2} x y)) && is32Bit(int64(off1)+int64(off2)) && canMergeSym(sym1, sym2) =>
1108 (LEAQ8 [off1+off2] {mergeSym(sym1,sym2)} x y)
1109
1110 // LEAQ[1248] into LEAQ[1248]. Only some such merges are possible.
1111 (LEAQ1 [off1] {sym1} x (LEAQ1 [off2] {sym2} y y)) && is32Bit(int64(off1)+int64(off2)) && canMergeSym(sym1, sym2) =>
1112 (LEAQ2 [off1+off2] {mergeSym(sym1, sym2)} x y)
1113 (LEAQ1 [off1] {sym1} x (LEAQ1 [off2] {sym2} x y)) && is32Bit(int64(off1)+int64(off2)) && canMergeSym(sym1, sym2) =>
1114 (LEAQ2 [off1+off2] {mergeSym(sym1, sym2)} y x)
1115 (LEAQ2 [off1] {sym1} x (LEAQ1 [off2] {sym2} y y)) && is32Bit(int64(off1)+2*int64(off2)) && sym2 == nil =>
1116 (LEAQ4 [off1+2*off2] {sym1} x y)
1117 (LEAQ4 [off1] {sym1} x (LEAQ1 [off2] {sym2} y y)) && is32Bit(int64(off1)+4*int64(off2)) && sym2 == nil =>
1118 (LEAQ8 [off1+4*off2] {sym1} x y)
1119 // TODO: more?
1120
1121 // Lower LEAQ2/4/8 when the offset is a constant
1122 (LEAQ2 [off] {sym} x (MOV(Q|L)const [scale])) && is32Bit(int64(off)+int64(scale)*2) =>
1123 (LEAQ [off+int32(scale)*2] {sym} x)
1124 (LEAQ4 [off] {sym} x (MOV(Q|L)const [scale])) && is32Bit(int64(off)+int64(scale)*4) =>
1125 (LEAQ [off+int32(scale)*4] {sym} x)
1126 (LEAQ8 [off] {sym} x (MOV(Q|L)const [scale])) && is32Bit(int64(off)+int64(scale)*8) =>
1127 (LEAQ [off+int32(scale)*8] {sym} x)
1128
1129 // Absorb InvertFlags into branches.
1130 (LT (InvertFlags cmp) yes no) => (GT cmp yes no)
1131 (GT (InvertFlags cmp) yes no) => (LT cmp yes no)
1132 (LE (InvertFlags cmp) yes no) => (GE cmp yes no)
1133 (GE (InvertFlags cmp) yes no) => (LE cmp yes no)
1134 (ULT (InvertFlags cmp) yes no) => (UGT cmp yes no)
1135 (UGT (InvertFlags cmp) yes no) => (ULT cmp yes no)
1136 (ULE (InvertFlags cmp) yes no) => (UGE cmp yes no)
1137 (UGE (InvertFlags cmp) yes no) => (ULE cmp yes no)
1138 (EQ (InvertFlags cmp) yes no) => (EQ cmp yes no)
1139 (NE (InvertFlags cmp) yes no) => (NE cmp yes no)
1140
1141 // Constant comparisons.
1142 (CMPQconst (MOVQconst [x]) [y]) && x==int64(y) => (FlagEQ)
1143 (CMPQconst (MOVQconst [x]) [y]) && x<int64(y) && uint64(x)<uint64(int64(y)) => (FlagLT_ULT)
1144 (CMPQconst (MOVQconst [x]) [y]) && x<int64(y) && uint64(x)>uint64(int64(y)) => (FlagLT_UGT)
1145 (CMPQconst (MOVQconst [x]) [y]) && x>int64(y) && uint64(x)<uint64(int64(y)) => (FlagGT_ULT)
1146 (CMPQconst (MOVQconst [x]) [y]) && x>int64(y) && uint64(x)>uint64(int64(y)) => (FlagGT_UGT)
1147 (CMPLconst (MOVLconst [x]) [y]) && x==y => (FlagEQ)
1148 (CMPLconst (MOVLconst [x]) [y]) && x<y && uint32(x)<uint32(y) => (FlagLT_ULT)
1149 (CMPLconst (MOVLconst [x]) [y]) && x<y && uint32(x)>uint32(y) => (FlagLT_UGT)
1150 (CMPLconst (MOVLconst [x]) [y]) && x>y && uint32(x)<uint32(y) => (FlagGT_ULT)
1151 (CMPLconst (MOVLconst [x]) [y]) && x>y && uint32(x)>uint32(y) => (FlagGT_UGT)
1152 (CMPWconst (MOVLconst [x]) [y]) && int16(x)==y => (FlagEQ)
1153 (CMPWconst (MOVLconst [x]) [y]) && int16(x)<y && uint16(x)<uint16(y) => (FlagLT_ULT)
1154 (CMPWconst (MOVLconst [x]) [y]) && int16(x)<y && uint16(x)>uint16(y) => (FlagLT_UGT)
1155 (CMPWconst (MOVLconst [x]) [y]) && int16(x)>y && uint16(x)<uint16(y) => (FlagGT_ULT)
1156 (CMPWconst (MOVLconst [x]) [y]) && int16(x)>y && uint16(x)>uint16(y) => (FlagGT_UGT)
1157 (CMPBconst (MOVLconst [x]) [y]) && int8(x)==y => (FlagEQ)
1158 (CMPBconst (MOVLconst [x]) [y]) && int8(x)<y && uint8(x)<uint8(y) => (FlagLT_ULT)
1159 (CMPBconst (MOVLconst [x]) [y]) && int8(x)<y && uint8(x)>uint8(y) => (FlagLT_UGT)
1160 (CMPBconst (MOVLconst [x]) [y]) && int8(x)>y && uint8(x)<uint8(y) => (FlagGT_ULT)
1161 (CMPBconst (MOVLconst [x]) [y]) && int8(x)>y && uint8(x)>uint8(y) => (FlagGT_UGT)
1162
1163 // CMPQconst requires a 32 bit const, but we can still constant-fold 64 bit consts.
1164 // In theory this applies to any of the simplifications above,
1165 // but CMPQ is the only one I've actually seen occur.
1166 (CMPQ (MOVQconst [x]) (MOVQconst [y])) && x==y => (FlagEQ)
1167 (CMPQ (MOVQconst [x]) (MOVQconst [y])) && x<y && uint64(x)<uint64(y) => (FlagLT_ULT)
1168 (CMPQ (MOVQconst [x]) (MOVQconst [y])) && x<y && uint64(x)>uint64(y) => (FlagLT_UGT)
1169 (CMPQ (MOVQconst [x]) (MOVQconst [y])) && x>y && uint64(x)<uint64(y) => (FlagGT_ULT)
1170 (CMPQ (MOVQconst [x]) (MOVQconst [y])) && x>y && uint64(x)>uint64(y) => (FlagGT_UGT)
1171
1172 // Other known comparisons.
1173 (CMPQconst (MOVBQZX _) [c]) && 0xFF < c => (FlagLT_ULT)
1174 (CMPQconst (MOVWQZX _) [c]) && 0xFFFF < c => (FlagLT_ULT)
1175 (CMPLconst (SHRLconst _ [c]) [n]) && 0 <= n && 0 < c && c <= 32 && (1<<uint64(32-c)) <= uint64(n) => (FlagLT_ULT)
1176 (CMPQconst (SHRQconst _ [c]) [n]) && 0 <= n && 0 < c && c <= 64 && (1<<uint64(64-c)) <= uint64(n) => (FlagLT_ULT)
1177 (CMPQconst (ANDQconst _ [m]) [n]) && 0 <= m && m < n => (FlagLT_ULT)
1178 (CMPQconst (ANDLconst _ [m]) [n]) && 0 <= m && m < n => (FlagLT_ULT)
1179 (CMPLconst (ANDLconst _ [m]) [n]) && 0 <= m && m < n => (FlagLT_ULT)
1180 (CMPWconst (ANDLconst _ [m]) [n]) && 0 <= int16(m) && int16(m) < n => (FlagLT_ULT)
1181 (CMPBconst (ANDLconst _ [m]) [n]) && 0 <= int8(m) && int8(m) < n => (FlagLT_ULT)
1182
1183 // TESTQ c c sets flags like CMPQ c 0.
1184 (TESTQconst [c] (MOVQconst [d])) && int64(c) == d && c == 0 => (FlagEQ)
1185 (TESTLconst [c] (MOVLconst [c])) && c == 0 => (FlagEQ)
1186 (TESTQconst [c] (MOVQconst [d])) && int64(c) == d && c < 0 => (FlagLT_UGT)
1187 (TESTLconst [c] (MOVLconst [c])) && c < 0 => (FlagLT_UGT)
1188 (TESTQconst [c] (MOVQconst [d])) && int64(c) == d && c > 0 => (FlagGT_UGT)
1189 (TESTLconst [c] (MOVLconst [c])) && c > 0 => (FlagGT_UGT)
1190
1191 // TODO: DIVxU also.
1192
1193 // Absorb flag constants into SBB ops.
1194 (SBBQcarrymask (FlagEQ)) => (MOVQconst [0])
1195 (SBBQcarrymask (FlagLT_ULT)) => (MOVQconst [-1])
1196 (SBBQcarrymask (FlagLT_UGT)) => (MOVQconst [0])
1197 (SBBQcarrymask (FlagGT_ULT)) => (MOVQconst [-1])
1198 (SBBQcarrymask (FlagGT_UGT)) => (MOVQconst [0])
1199 (SBBLcarrymask (FlagEQ)) => (MOVLconst [0])
1200 (SBBLcarrymask (FlagLT_ULT)) => (MOVLconst [-1])
1201 (SBBLcarrymask (FlagLT_UGT)) => (MOVLconst [0])
1202 (SBBLcarrymask (FlagGT_ULT)) => (MOVLconst [-1])
1203 (SBBLcarrymask (FlagGT_UGT)) => (MOVLconst [0])
1204
1205 // Absorb flag constants into branches.
1206 ((EQ|LE|GE|ULE|UGE) (FlagEQ) yes no) => (First yes no)
1207 ((NE|LT|GT|ULT|UGT) (FlagEQ) yes no) => (First no yes)
1208 ((NE|LT|LE|ULT|ULE) (FlagLT_ULT) yes no) => (First yes no)
1209 ((EQ|GT|GE|UGT|UGE) (FlagLT_ULT) yes no) => (First no yes)
1210 ((NE|LT|LE|UGT|UGE) (FlagLT_UGT) yes no) => (First yes no)
1211 ((EQ|GT|GE|ULT|ULE) (FlagLT_UGT) yes no) => (First no yes)
1212 ((NE|GT|GE|ULT|ULE) (FlagGT_ULT) yes no) => (First yes no)
1213 ((EQ|LT|LE|UGT|UGE) (FlagGT_ULT) yes no) => (First no yes)
1214 ((NE|GT|GE|UGT|UGE) (FlagGT_UGT) yes no) => (First yes no)
1215 ((EQ|LT|LE|ULT|ULE) (FlagGT_UGT) yes no) => (First no yes)
1216
1217 // Absorb flag constants into SETxx ops.
1218 ((SETEQ|SETLE|SETGE|SETBE|SETAE) (FlagEQ)) => (MOVLconst [1])
1219 ((SETNE|SETL|SETG|SETB|SETA) (FlagEQ)) => (MOVLconst [0])
1220 ((SETNE|SETL|SETLE|SETB|SETBE) (FlagLT_ULT)) => (MOVLconst [1])
1221 ((SETEQ|SETG|SETGE|SETA|SETAE) (FlagLT_ULT)) => (MOVLconst [0])
1222 ((SETNE|SETL|SETLE|SETA|SETAE) (FlagLT_UGT)) => (MOVLconst [1])
1223 ((SETEQ|SETG|SETGE|SETB|SETBE) (FlagLT_UGT)) => (MOVLconst [0])
1224 ((SETNE|SETG|SETGE|SETB|SETBE) (FlagGT_ULT)) => (MOVLconst [1])
1225 ((SETEQ|SETL|SETLE|SETA|SETAE) (FlagGT_ULT)) => (MOVLconst [0])
1226 ((SETNE|SETG|SETGE|SETA|SETAE) (FlagGT_UGT)) => (MOVLconst [1])
1227 ((SETEQ|SETL|SETLE|SETB|SETBE) (FlagGT_UGT)) => (MOVLconst [0])
1228
1229 (SETEQstore [off] {sym} ptr (FlagEQ) mem) => (MOVBstore [off] {sym} ptr (MOVLconst <typ.UInt8> [1]) mem)
1230 (SETEQstore [off] {sym} ptr (FlagLT_ULT) mem) => (MOVBstore [off] {sym} ptr (MOVLconst <typ.UInt8> [0]) mem)
1231 (SETEQstore [off] {sym} ptr (FlagLT_UGT) mem) => (MOVBstore [off] {sym} ptr (MOVLconst <typ.UInt8> [0]) mem)
1232 (SETEQstore [off] {sym} ptr (FlagGT_ULT) mem) => (MOVBstore [off] {sym} ptr (MOVLconst <typ.UInt8> [0]) mem)
1233 (SETEQstore [off] {sym} ptr (FlagGT_UGT) mem) => (MOVBstore [off] {sym} ptr (MOVLconst <typ.UInt8> [0]) mem)
1234
1235 (SETNEstore [off] {sym} ptr (FlagEQ) mem) => (MOVBstore [off] {sym} ptr (MOVLconst <typ.UInt8> [0]) mem)
1236 (SETNEstore [off] {sym} ptr (FlagLT_ULT) mem) => (MOVBstore [off] {sym} ptr (MOVLconst <typ.UInt8> [1]) mem)
1237 (SETNEstore [off] {sym} ptr (FlagLT_UGT) mem) => (MOVBstore [off] {sym} ptr (MOVLconst <typ.UInt8> [1]) mem)
1238 (SETNEstore [off] {sym} ptr (FlagGT_ULT) mem) => (MOVBstore [off] {sym} ptr (MOVLconst <typ.UInt8> [1]) mem)
1239 (SETNEstore [off] {sym} ptr (FlagGT_UGT) mem) => (MOVBstore [off] {sym} ptr (MOVLconst <typ.UInt8> [1]) mem)
1240
1241 (SETLstore [off] {sym} ptr (FlagEQ) mem) => (MOVBstore [off] {sym} ptr (MOVLconst <typ.UInt8> [0]) mem)
1242 (SETLstore [off] {sym} ptr (FlagLT_ULT) mem) => (MOVBstore [off] {sym} ptr (MOVLconst <typ.UInt8> [1]) mem)
1243 (SETLstore [off] {sym} ptr (FlagLT_UGT) mem) => (MOVBstore [off] {sym} ptr (MOVLconst <typ.UInt8> [1]) mem)
1244 (SETLstore [off] {sym} ptr (FlagGT_ULT) mem) => (MOVBstore [off] {sym} ptr (MOVLconst <typ.UInt8> [0]) mem)
1245 (SETLstore [off] {sym} ptr (FlagGT_UGT) mem) => (MOVBstore [off] {sym} ptr (MOVLconst <typ.UInt8> [0]) mem)
1246
1247 (SETLEstore [off] {sym} ptr (FlagEQ) mem) => (MOVBstore [off] {sym} ptr (MOVLconst <typ.UInt8> [1]) mem)
1248 (SETLEstore [off] {sym} ptr (FlagLT_ULT) mem) => (MOVBstore [off] {sym} ptr (MOVLconst <typ.UInt8> [1]) mem)
1249 (SETLEstore [off] {sym} ptr (FlagLT_UGT) mem) => (MOVBstore [off] {sym} ptr (MOVLconst <typ.UInt8> [1]) mem)
1250 (SETLEstore [off] {sym} ptr (FlagGT_ULT) mem) => (MOVBstore [off] {sym} ptr (MOVLconst <typ.UInt8> [0]) mem)
1251 (SETLEstore [off] {sym} ptr (FlagGT_UGT) mem) => (MOVBstore [off] {sym} ptr (MOVLconst <typ.UInt8> [0]) mem)
1252
1253 (SETGstore [off] {sym} ptr (FlagEQ) mem) => (MOVBstore [off] {sym} ptr (MOVLconst <typ.UInt8> [0]) mem)
1254 (SETGstore [off] {sym} ptr (FlagLT_ULT) mem) => (MOVBstore [off] {sym} ptr (MOVLconst <typ.UInt8> [0]) mem)
1255 (SETGstore [off] {sym} ptr (FlagLT_UGT) mem) => (MOVBstore [off] {sym} ptr (MOVLconst <typ.UInt8> [0]) mem)
1256 (SETGstore [off] {sym} ptr (FlagGT_ULT) mem) => (MOVBstore [off] {sym} ptr (MOVLconst <typ.UInt8> [1]) mem)
1257 (SETGstore [off] {sym} ptr (FlagGT_UGT) mem) => (MOVBstore [off] {sym} ptr (MOVLconst <typ.UInt8> [1]) mem)
1258
1259 (SETGEstore [off] {sym} ptr (FlagEQ) mem) => (MOVBstore [off] {sym} ptr (MOVLconst <typ.UInt8> [1]) mem)
1260 (SETGEstore [off] {sym} ptr (FlagLT_ULT) mem) => (MOVBstore [off] {sym} ptr (MOVLconst <typ.UInt8> [0]) mem)
1261 (SETGEstore [off] {sym} ptr (FlagLT_UGT) mem) => (MOVBstore [off] {sym} ptr (MOVLconst <typ.UInt8> [0]) mem)
1262 (SETGEstore [off] {sym} ptr (FlagGT_ULT) mem) => (MOVBstore [off] {sym} ptr (MOVLconst <typ.UInt8> [1]) mem)
1263 (SETGEstore [off] {sym} ptr (FlagGT_UGT) mem) => (MOVBstore [off] {sym} ptr (MOVLconst <typ.UInt8> [1]) mem)
1264
1265 (SETBstore [off] {sym} ptr (FlagEQ) mem) => (MOVBstore [off] {sym} ptr (MOVLconst <typ.UInt8> [0]) mem)
1266 (SETBstore [off] {sym} ptr (FlagLT_ULT) mem) => (MOVBstore [off] {sym} ptr (MOVLconst <typ.UInt8> [1]) mem)
1267 (SETBstore [off] {sym} ptr (FlagLT_UGT) mem) => (MOVBstore [off] {sym} ptr (MOVLconst <typ.UInt8> [0]) mem)
1268 (SETBstore [off] {sym} ptr (FlagGT_ULT) mem) => (MOVBstore [off] {sym} ptr (MOVLconst <typ.UInt8> [1]) mem)
1269 (SETBstore [off] {sym} ptr (FlagGT_UGT) mem) => (MOVBstore [off] {sym} ptr (MOVLconst <typ.UInt8> [0]) mem)
1270
1271 (SETBEstore [off] {sym} ptr (FlagEQ) mem) => (MOVBstore [off] {sym} ptr (MOVLconst <typ.UInt8> [1]) mem)
1272 (SETBEstore [off] {sym} ptr (FlagLT_ULT) mem) => (MOVBstore [off] {sym} ptr (MOVLconst <typ.UInt8> [1]) mem)
1273 (SETBEstore [off] {sym} ptr (FlagLT_UGT) mem) => (MOVBstore [off] {sym} ptr (MOVLconst <typ.UInt8> [0]) mem)
1274 (SETBEstore [off] {sym} ptr (FlagGT_ULT) mem) => (MOVBstore [off] {sym} ptr (MOVLconst <typ.UInt8> [1]) mem)
1275 (SETBEstore [off] {sym} ptr (FlagGT_UGT) mem) => (MOVBstore [off] {sym} ptr (MOVLconst <typ.UInt8> [0]) mem)
1276
1277 (SETAstore [off] {sym} ptr (FlagEQ) mem) => (MOVBstore [off] {sym} ptr (MOVLconst <typ.UInt8> [0]) mem)
1278 (SETAstore [off] {sym} ptr (FlagLT_ULT) mem) => (MOVBstore [off] {sym} ptr (MOVLconst <typ.UInt8> [0]) mem)
1279 (SETAstore [off] {sym} ptr (FlagLT_UGT) mem) => (MOVBstore [off] {sym} ptr (MOVLconst <typ.UInt8> [1]) mem)
1280 (SETAstore [off] {sym} ptr (FlagGT_ULT) mem) => (MOVBstore [off] {sym} ptr (MOVLconst <typ.UInt8> [0]) mem)
1281 (SETAstore [off] {sym} ptr (FlagGT_UGT) mem) => (MOVBstore [off] {sym} ptr (MOVLconst <typ.UInt8> [1]) mem)
1282
1283 (SETAEstore [off] {sym} ptr (FlagEQ) mem) => (MOVBstore [off] {sym} ptr (MOVLconst <typ.UInt8> [1]) mem)
1284 (SETAEstore [off] {sym} ptr (FlagLT_ULT) mem) => (MOVBstore [off] {sym} ptr (MOVLconst <typ.UInt8> [0]) mem)
1285 (SETAEstore [off] {sym} ptr (FlagLT_UGT) mem) => (MOVBstore [off] {sym} ptr (MOVLconst <typ.UInt8> [1]) mem)
1286 (SETAEstore [off] {sym} ptr (FlagGT_ULT) mem) => (MOVBstore [off] {sym} ptr (MOVLconst <typ.UInt8> [0]) mem)
1287 (SETAEstore [off] {sym} ptr (FlagGT_UGT) mem) => (MOVBstore [off] {sym} ptr (MOVLconst <typ.UInt8> [1]) mem)
1288
1289 // Remove redundant *const ops
1290 (ADD(Q|L)const [0] x) => x
1291 (SUB(Q|L)const [0] x) => x
1292 (AND(Q|L)const [0] _) => (MOVLconst [0])
1293 (AND(Q|L)const [-1] x) => x
1294 (OR(Q|L)const [0] x) => x
1295 (OR(Q|L)const [-1] _) => (MOV(Q|L)const [-1])
1296 (XOR(Q|L)const [0] x) => x
1297 // TODO: since we got rid of the W/B versions, we might miss
1298 // things like (ANDLconst [0x100] x) which were formerly
1299 // (ANDBconst [0] x). Probably doesn't happen very often.
1300 // If we cared, we might do:
1301 // (ANDLconst <t> [c] x) && t.Size()==1 && int8(x)==0 -> (MOVLconst [0])
1302
1303 // Remove redundant ops
1304 // Not in generic rules, because they may appear after lowering e. g. Slicemask
1305 (NEG(Q|L) (NEG(Q|L) x)) => x
1306 (NEG(Q|L) s:(SUB(Q|L) x y)) && s.Uses == 1 => (SUB(Q|L) y x)
1307
1308 // Convert constant subtracts to constant adds
1309 (SUBQconst [c] x) && c != -(1<<31) => (ADDQconst [-c] x)
1310 (SUBLconst [c] x) => (ADDLconst [-c] x)
1311
1312 // generic constant folding
1313 // TODO: more of this
1314 (ADDQconst [c] (MOVQconst [d])) => (MOVQconst [int64(c)+d])
1315 (ADDLconst [c] (MOVLconst [d])) => (MOVLconst [c+d])
1316 (ADDQconst [c] (ADDQconst [d] x)) && is32Bit(int64(c)+int64(d)) => (ADDQconst [c+d] x)
1317 (ADDLconst [c] (ADDLconst [d] x)) => (ADDLconst [c+d] x)
1318 (SUBQconst (MOVQconst [d]) [c]) => (MOVQconst [d-int64(c)])
1319 (SUBQconst (SUBQconst x [d]) [c]) && is32Bit(int64(-c)-int64(d)) => (ADDQconst [-c-d] x)
1320 (SARQconst [c] (MOVQconst [d])) => (MOVQconst [d>>uint64(c)])
1321 (SARLconst [c] (MOVQconst [d])) => (MOVQconst [int64(int32(d))>>uint64(c)])
1322 (SARWconst [c] (MOVQconst [d])) => (MOVQconst [int64(int16(d))>>uint64(c)])
1323 (SARBconst [c] (MOVQconst [d])) => (MOVQconst [int64(int8(d))>>uint64(c)])
1324 (NEG(Q|L) (MOV(Q|L)const [c])) => (MOV(Q|L)const [-c])
1325 (MULQconst [c] (MOVQconst [d])) => (MOVQconst [int64(c)*d])
1326 (MULLconst [c] (MOVLconst [d])) => (MOVLconst [c*d])
1327 (ANDQconst [c] (MOVQconst [d])) => (MOVQconst [int64(c)&d])
1328 (ANDLconst [c] (MOVLconst [d])) => (MOVLconst [c&d])
1329 (ORQconst [c] (MOVQconst [d])) => (MOVQconst [int64(c)|d])
1330 (ORLconst [c] (MOVLconst [d])) => (MOVLconst [c|d])
1331 (XORQconst [c] (MOVQconst [d])) => (MOVQconst [int64(c)^d])
1332 (XORLconst [c] (MOVLconst [d])) => (MOVLconst [c^d])
1333 (NOT(Q|L) (MOV(Q|L)const [c])) => (MOV(Q|L)const [^c])
1334 (BTSQconst [c] (MOVQconst [d])) => (MOVQconst [d|(1<<uint32(c))])
1335 (BTRQconst [c] (MOVQconst [d])) => (MOVQconst [d&^(1<<uint32(c))])
1336 (BTCQconst [c] (MOVQconst [d])) => (MOVQconst [d^(1<<uint32(c))])
1337
1338 // If c or d doesn't fit into 32 bits, then we can't construct ORQconst,
1339 // but we can still constant-fold.
1340 // In theory this applies to any of the simplifications above,
1341 // but ORQ is the only one I've actually seen occur.
1342 (ORQ (MOVQconst [c]) (MOVQconst [d])) => (MOVQconst [c|d])
1343
1344 // generic simplifications
1345 // TODO: more of this
1346 (ADD(Q|L) x (NEG(Q|L) y)) => (SUB(Q|L) x y)
1347 (SUB(Q|L) x x) => (MOVLconst [0])
1348 (AND(Q|L) x x) => x
1349 (OR(Q|L) x x) => x
1350 (XOR(Q|L) x x) => (MOVLconst [0])
1351
1352 (SHLLconst [d] (MOVLconst [c])) => (MOVLconst [c << uint64(d)])
1353 (SHLQconst [d] (MOVQconst [c])) => (MOVQconst [c << uint64(d)])
1354 (SHLQconst [d] (MOVLconst [c])) => (MOVQconst [int64(c) << uint64(d)])
1355
1356 // Fold NEG into ADDconst/MULconst. Take care to keep c in 32 bit range.
1357 (NEGQ (ADDQconst [c] (NEGQ x))) && c != -(1<<31) => (ADDQconst [-c] x)
1358 (MULQconst [c] (NEGQ x)) && c != -(1<<31) => (MULQconst [-c] x)
1359
1360 // checking AND against 0.
1361 (CMP(Q|L|W|B)const a:(AND(Q|L|L|L) x y) [0]) && a.Uses == 1 => (TEST(Q|L|W|B) x y)
1362 (CMPQconst a:(ANDQconst [c] x) [0]) && a.Uses == 1 => (TESTQconst [c] x)
1363 (CMPLconst a:(ANDLconst [c] x) [0]) && a.Uses == 1 => (TESTLconst [c] x)
1364 (CMPWconst a:(ANDLconst [c] x) [0]) && a.Uses == 1 => (TESTWconst [int16(c)] x)
1365 (CMPBconst a:(ANDLconst [c] x) [0]) && a.Uses == 1 => (TESTBconst [int8(c)] x)
1366
1367 // Convert TESTx to TESTxconst if possible.
1368 (TESTQ (MOVQconst [c]) x) && is32Bit(c) => (TESTQconst [int32(c)] x)
1369 (TESTL (MOVLconst [c]) x) => (TESTLconst [c] x)
1370 (TESTW (MOVLconst [c]) x) => (TESTWconst [int16(c)] x)
1371 (TESTB (MOVLconst [c]) x) => (TESTBconst [int8(c)] x)
1372
1373 // TEST %reg,%reg is shorter than CMP
1374 (CMP(Q|L|W|B)const x [0]) => (TEST(Q|L|W|B) x x)
1375 (TESTQconst [-1] x) && x.Op != OpAMD64MOVQconst => (TESTQ x x)
1376 (TESTLconst [-1] x) && x.Op != OpAMD64MOVLconst => (TESTL x x)
1377 (TESTWconst [-1] x) && x.Op != OpAMD64MOVLconst => (TESTW x x)
1378 (TESTBconst [-1] x) && x.Op != OpAMD64MOVLconst => (TESTB x x)
1379
1380 // Convert LEAQ1 back to ADDQ if we can
1381 (LEAQ1 [0] x y) && v.Aux == nil => (ADDQ x y)
1382
1383 (MOVQstoreconst [c] {s} p1 x:(MOVQstoreconst [a] {s} p0 mem))
1384 && x.Uses == 1
1385 && sequentialAddresses(p0, p1, int64(a.Off()+8-c.Off()))
1386 && a.Val() == 0
1387 && c.Val() == 0
1388 && setPos(v, x.Pos)
1389 && clobber(x)
1390 => (MOVOstoreconst [makeValAndOff(0,a.Off())] {s} p0 mem)
1391 (MOVQstoreconst [a] {s} p0 x:(MOVQstoreconst [c] {s} p1 mem))
1392 && x.Uses == 1
1393 && sequentialAddresses(p0, p1, int64(a.Off()+8-c.Off()))
1394 && a.Val() == 0
1395 && c.Val() == 0
1396 && setPos(v, x.Pos)
1397 && clobber(x)
1398 => (MOVOstoreconst [makeValAndOff(0,a.Off())] {s} p0 mem)
1399
1400 // Merge load and op
1401 // TODO: add indexed variants?
1402 ((ADD|SUB|AND|OR|XOR)Q x l:(MOVQload [off] {sym} ptr mem)) && canMergeLoadClobber(v, l, x) && clobber(l) => ((ADD|SUB|AND|OR|XOR)Qload x [off] {sym} ptr mem)
1403 ((ADD|SUB|AND|OR|XOR)L x l:(MOVLload [off] {sym} ptr mem)) && canMergeLoadClobber(v, l, x) && clobber(l) => ((ADD|SUB|AND|OR|XOR)Lload x [off] {sym} ptr mem)
1404 ((ADD|SUB|MUL|DIV)SD x l:(MOVSDload [off] {sym} ptr mem)) && canMergeLoadClobber(v, l, x) && clobber(l) => ((ADD|SUB|MUL|DIV)SDload x [off] {sym} ptr mem)
1405 ((ADD|SUB|MUL|DIV)SS x l:(MOVSSload [off] {sym} ptr mem)) && canMergeLoadClobber(v, l, x) && clobber(l) => ((ADD|SUB|MUL|DIV)SSload x [off] {sym} ptr mem)
1406 (MOVLstore {sym} [off] ptr y:((ADD|AND|OR|XOR)Lload x [off] {sym} ptr mem) mem) && y.Uses==1 && clobber(y) => ((ADD|AND|OR|XOR)Lmodify [off] {sym} ptr x mem)
1407 (MOVLstore {sym} [off] ptr y:((ADD|SUB|AND|OR|XOR)L l:(MOVLload [off] {sym} ptr mem) x) mem) && y.Uses==1 && l.Uses==1 && clobber(y, l) =>
1408 ((ADD|SUB|AND|OR|XOR)Lmodify [off] {sym} ptr x mem)
1409 (MOVQstore {sym} [off] ptr y:((ADD|AND|OR|XOR)Qload x [off] {sym} ptr mem) mem) && y.Uses==1 && clobber(y) => ((ADD|AND|OR|XOR)Qmodify [off] {sym} ptr x mem)
1410 (MOVQstore {sym} [off] ptr y:((ADD|SUB|AND|OR|XOR)Q l:(MOVQload [off] {sym} ptr mem) x) mem) && y.Uses==1 && l.Uses==1 && clobber(y, l) =>
1411 ((ADD|SUB|AND|OR|XOR)Qmodify [off] {sym} ptr x mem)
1412 (MOVQstore {sym} [off] ptr x:(BT(S|R|C)Qconst [c] l:(MOVQload {sym} [off] ptr mem)) mem) && x.Uses == 1 && l.Uses == 1 && clobber(x, l) =>
1413 (BT(S|R|C)Qconstmodify {sym} [makeValAndOff(int32(c),off)] ptr mem)
1414
1415 // Merge ADDQconst and LEAQ into atomic loads.
1416 (MOV(Q|L|B)atomicload [off1] {sym} (ADDQconst [off2] ptr) mem) && is32Bit(int64(off1)+int64(off2)) =>
1417 (MOV(Q|L|B)atomicload [off1+off2] {sym} ptr mem)
1418 (MOV(Q|L|B)atomicload [off1] {sym1} (LEAQ [off2] {sym2} ptr) mem) && is32Bit(int64(off1)+int64(off2)) && canMergeSym(sym1, sym2) =>
1419 (MOV(Q|L|B)atomicload [off1+off2] {mergeSym(sym1, sym2)} ptr mem)
1420
1421 // Merge ADDQconst and LEAQ into atomic stores.
1422 (XCHGQ [off1] {sym} val (ADDQconst [off2] ptr) mem) && is32Bit(int64(off1)+int64(off2)) =>
1423 (XCHGQ [off1+off2] {sym} val ptr mem)
1424 (XCHGQ [off1] {sym1} val (LEAQ [off2] {sym2} ptr) mem) && is32Bit(int64(off1)+int64(off2)) && canMergeSym(sym1, sym2) && ptr.Op != OpSB =>
1425 (XCHGQ [off1+off2] {mergeSym(sym1,sym2)} val ptr mem)
1426 (XCHGL [off1] {sym} val (ADDQconst [off2] ptr) mem) && is32Bit(int64(off1)+int64(off2)) =>
1427 (XCHGL [off1+off2] {sym} val ptr mem)
1428 (XCHGL [off1] {sym1} val (LEAQ [off2] {sym2} ptr) mem) && is32Bit(int64(off1)+int64(off2)) && canMergeSym(sym1, sym2) && ptr.Op != OpSB =>
1429 (XCHGL [off1+off2] {mergeSym(sym1,sym2)} val ptr mem)
1430
1431 // Merge ADDQconst into atomic adds.
1432 // TODO: merging LEAQ doesn't work, assembler doesn't like the resulting instructions.
1433 (XADDQlock [off1] {sym} val (ADDQconst [off2] ptr) mem) && is32Bit(int64(off1)+int64(off2)) =>
1434 (XADDQlock [off1+off2] {sym} val ptr mem)
1435 (XADDLlock [off1] {sym} val (ADDQconst [off2] ptr) mem) && is32Bit(int64(off1)+int64(off2)) =>
1436 (XADDLlock [off1+off2] {sym} val ptr mem)
1437
1438 // Merge ADDQconst into atomic compare and swaps.
1439 // TODO: merging LEAQ doesn't work, assembler doesn't like the resulting instructions.
1440 (CMPXCHGQlock [off1] {sym} (ADDQconst [off2] ptr) old new_ mem) && is32Bit(int64(off1)+int64(off2)) =>
1441 (CMPXCHGQlock [off1+off2] {sym} ptr old new_ mem)
1442 (CMPXCHGLlock [off1] {sym} (ADDQconst [off2] ptr) old new_ mem) && is32Bit(int64(off1)+int64(off2)) =>
1443 (CMPXCHGLlock [off1+off2] {sym} ptr old new_ mem)
1444
1445 // We don't need the conditional move if we know the arg of BSF is not zero.
1446 (CMOVQEQ x _ (Select1 (BS(F|R)Q (ORQconst [c] _)))) && c != 0 => x
1447 // Extension is unnecessary for trailing zeros.
1448 (BSFQ (ORQconst <t> [1<<8] (MOVBQZX x))) => (BSFQ (ORQconst <t> [1<<8] x))
1449 (BSFQ (ORQconst <t> [1<<16] (MOVWQZX x))) => (BSFQ (ORQconst <t> [1<<16] x))
1450
1451 // Redundant sign/zero extensions
1452 // Note: see issue 21963. We have to make sure we use the right type on
1453 // the resulting extension (the outer type, not the inner type).
1454 (MOVLQSX (MOVLQSX x)) => (MOVLQSX x)
1455 (MOVLQSX (MOVWQSX x)) => (MOVWQSX x)
1456 (MOVLQSX (MOVBQSX x)) => (MOVBQSX x)
1457 (MOVWQSX (MOVWQSX x)) => (MOVWQSX x)
1458 (MOVWQSX (MOVBQSX x)) => (MOVBQSX x)
1459 (MOVBQSX (MOVBQSX x)) => (MOVBQSX x)
1460 (MOVLQZX (MOVLQZX x)) => (MOVLQZX x)
1461 (MOVLQZX (MOVWQZX x)) => (MOVWQZX x)
1462 (MOVLQZX (MOVBQZX x)) => (MOVBQZX x)
1463 (MOVWQZX (MOVWQZX x)) => (MOVWQZX x)
1464 (MOVWQZX (MOVBQZX x)) => (MOVBQZX x)
1465 (MOVBQZX (MOVBQZX x)) => (MOVBQZX x)
1466
1467 (MOVQstore [off] {sym} ptr a:((ADD|AND|OR|XOR)Qconst [c] l:(MOVQload [off] {sym} ptr2 mem)) mem)
1468 && isSamePtr(ptr, ptr2) && a.Uses == 1 && l.Uses == 1 && clobber(l, a) =>
1469 ((ADD|AND|OR|XOR)Qconstmodify {sym} [makeValAndOff(int32(c),off)] ptr mem)
1470 (MOVLstore [off] {sym} ptr a:((ADD|AND|OR|XOR)Lconst [c] l:(MOVLload [off] {sym} ptr2 mem)) mem)
1471 && isSamePtr(ptr, ptr2) && a.Uses == 1 && l.Uses == 1 && clobber(l, a) =>
1472 ((ADD|AND|OR|XOR)Lconstmodify {sym} [makeValAndOff(int32(c),off)] ptr mem)
1473
1474 // float <-> int register moves, with no conversion.
1475 // These come up when compiling math.{Float{32,64}bits,Float{32,64}frombits}.
1476 (MOVQload [off] {sym} ptr (MOVSDstore [off] {sym} ptr val _)) => (MOVQf2i val)
1477 (MOVLload [off] {sym} ptr (MOVSSstore [off] {sym} ptr val _)) => (MOVLf2i val)
1478 (MOVSDload [off] {sym} ptr (MOVQstore [off] {sym} ptr val _)) => (MOVQi2f val)
1479 (MOVSSload [off] {sym} ptr (MOVLstore [off] {sym} ptr val _)) => (MOVLi2f val)
1480
1481 // Other load-like ops.
1482 (ADDQload x [off] {sym} ptr (MOVSDstore [off] {sym} ptr y _)) => (ADDQ x (MOVQf2i y))
1483 (ADDLload x [off] {sym} ptr (MOVSSstore [off] {sym} ptr y _)) => (ADDL x (MOVLf2i y))
1484 (SUBQload x [off] {sym} ptr (MOVSDstore [off] {sym} ptr y _)) => (SUBQ x (MOVQf2i y))
1485 (SUBLload x [off] {sym} ptr (MOVSSstore [off] {sym} ptr y _)) => (SUBL x (MOVLf2i y))
1486 (ANDQload x [off] {sym} ptr (MOVSDstore [off] {sym} ptr y _)) => (ANDQ x (MOVQf2i y))
1487 (ANDLload x [off] {sym} ptr (MOVSSstore [off] {sym} ptr y _)) => (ANDL x (MOVLf2i y))
1488 ( ORQload x [off] {sym} ptr (MOVSDstore [off] {sym} ptr y _)) => ( ORQ x (MOVQf2i y))
1489 ( ORLload x [off] {sym} ptr (MOVSSstore [off] {sym} ptr y _)) => ( ORL x (MOVLf2i y))
1490 (XORQload x [off] {sym} ptr (MOVSDstore [off] {sym} ptr y _)) => (XORQ x (MOVQf2i y))
1491 (XORLload x [off] {sym} ptr (MOVSSstore [off] {sym} ptr y _)) => (XORL x (MOVLf2i y))
1492
1493 (ADDSDload x [off] {sym} ptr (MOVQstore [off] {sym} ptr y _)) => (ADDSD x (MOVQi2f y))
1494 (ADDSSload x [off] {sym} ptr (MOVLstore [off] {sym} ptr y _)) => (ADDSS x (MOVLi2f y))
1495 (SUBSDload x [off] {sym} ptr (MOVQstore [off] {sym} ptr y _)) => (SUBSD x (MOVQi2f y))
1496 (SUBSSload x [off] {sym} ptr (MOVLstore [off] {sym} ptr y _)) => (SUBSS x (MOVLi2f y))
1497 (MULSDload x [off] {sym} ptr (MOVQstore [off] {sym} ptr y _)) => (MULSD x (MOVQi2f y))
1498 (MULSSload x [off] {sym} ptr (MOVLstore [off] {sym} ptr y _)) => (MULSS x (MOVLi2f y))
1499
1500 // Detect FMA
1501 (ADDS(S|D) (MULS(S|D) x y) z) && buildcfg.GOAMD64 >= 3 && z.Block.Func.useFMA(v) => (VFMADD231S(S|D) z x y)
1502
1503 // Redirect stores to use the other register set.
1504 (MOVQstore [off] {sym} ptr (MOVQf2i val) mem) => (MOVSDstore [off] {sym} ptr val mem)
1505 (MOVLstore [off] {sym} ptr (MOVLf2i val) mem) => (MOVSSstore [off] {sym} ptr val mem)
1506 (MOVSDstore [off] {sym} ptr (MOVQi2f val) mem) => (MOVQstore [off] {sym} ptr val mem)
1507 (MOVSSstore [off] {sym} ptr (MOVLi2f val) mem) => (MOVLstore [off] {sym} ptr val mem)
1508
1509 (MOVSDstore [off] {sym} ptr (MOVSDconst [f]) mem) && f == f => (MOVQstore [off] {sym} ptr (MOVQconst [int64(math.Float64bits(f))]) mem)
1510 (MOVSSstore [off] {sym} ptr (MOVSSconst [f]) mem) && f == f => (MOVLstore [off] {sym} ptr (MOVLconst [int32(math.Float32bits(f))]) mem)
1511
1512 // Load args directly into the register class where it will be used.
1513 // We do this by just modifying the type of the Arg.
1514 (MOVQf2i <t> (Arg <u> [off] {sym})) && t.Size() == u.Size() => @b.Func.Entry (Arg <t> [off] {sym})
1515 (MOVLf2i <t> (Arg <u> [off] {sym})) && t.Size() == u.Size() => @b.Func.Entry (Arg <t> [off] {sym})
1516 (MOVQi2f <t> (Arg <u> [off] {sym})) && t.Size() == u.Size() => @b.Func.Entry (Arg <t> [off] {sym})
1517 (MOVLi2f <t> (Arg <u> [off] {sym})) && t.Size() == u.Size() => @b.Func.Entry (Arg <t> [off] {sym})
1518
1519 // LEAQ is rematerializeable, so this helps to avoid register spill.
1520 // See issue 22947 for details
1521 (ADD(Q|L)const [off] x:(SP)) => (LEA(Q|L) [off] x)
1522
1523 // HMULx is commutative, but its first argument must go in AX.
1524 // If possible, put a rematerializeable value in the first argument slot,
1525 // to reduce the odds that another value will be have to spilled
1526 // specifically to free up AX.
1527 (HMUL(Q|L) x y) && !x.rematerializeable() && y.rematerializeable() => (HMUL(Q|L) y x)
1528 (HMUL(Q|L)U x y) && !x.rematerializeable() && y.rematerializeable() => (HMUL(Q|L)U y x)
1529
1530 // Fold loads into compares
1531 // Note: these may be undone by the flagalloc pass.
1532 (CMP(Q|L|W|B) l:(MOV(Q|L|W|B)load {sym} [off] ptr mem) x) && canMergeLoad(v, l) && clobber(l) => (CMP(Q|L|W|B)load {sym} [off] ptr x mem)
1533 (CMP(Q|L|W|B) x l:(MOV(Q|L|W|B)load {sym} [off] ptr mem)) && canMergeLoad(v, l) && clobber(l) => (InvertFlags (CMP(Q|L|W|B)load {sym} [off] ptr x mem))
1534
1535 (CMP(Q|L)const l:(MOV(Q|L)load {sym} [off] ptr mem) [c])
1536 && l.Uses == 1
1537 && clobber(l) =>
1538 @l.Block (CMP(Q|L)constload {sym} [makeValAndOff(c,off)] ptr mem)
1539 (CMP(W|B)const l:(MOV(W|B)load {sym} [off] ptr mem) [c])
1540 && l.Uses == 1
1541 && clobber(l) =>
1542 @l.Block (CMP(W|B)constload {sym} [makeValAndOff(int32(c),off)] ptr mem)
1543
1544 (CMPQload {sym} [off] ptr (MOVQconst [c]) mem) && validVal(c) => (CMPQconstload {sym} [makeValAndOff(int32(c),off)] ptr mem)
1545 (CMPLload {sym} [off] ptr (MOVLconst [c]) mem) => (CMPLconstload {sym} [makeValAndOff(c,off)] ptr mem)
1546 (CMPWload {sym} [off] ptr (MOVLconst [c]) mem) => (CMPWconstload {sym} [makeValAndOff(int32(int16(c)),off)] ptr mem)
1547 (CMPBload {sym} [off] ptr (MOVLconst [c]) mem) => (CMPBconstload {sym} [makeValAndOff(int32(int8(c)),off)] ptr mem)
1548
1549 (TEST(Q|L|W|B) l:(MOV(Q|L|W|B)load {sym} [off] ptr mem) l2)
1550 && l == l2
1551 && l.Uses == 2
1552 && clobber(l) =>
1553 @l.Block (CMP(Q|L|W|B)constload {sym} [makeValAndOff(0, off)] ptr mem)
1554
1555 // Convert ANDload to MOVload when we can do the AND in a containing TEST op.
1556 // Only do when it's within the same block, so we don't have flags live across basic block boundaries.
1557 // See issue 44228.
1558 (TEST(Q|L) a:(AND(Q|L)load [off] {sym} x ptr mem) a) && a.Uses == 2 && a.Block == v.Block && clobber(a) => (TEST(Q|L) (MOV(Q|L)load <a.Type> [off] {sym} ptr mem) x)
1559
1560 (MOVBload [off] {sym} (SB) _) && symIsRO(sym) => (MOVLconst [int32(read8(sym, int64(off)))])
1561 (MOVWload [off] {sym} (SB) _) && symIsRO(sym) => (MOVLconst [int32(read16(sym, int64(off), config.ctxt.Arch.ByteOrder))])
1562 (MOVLload <t> [off] {sym} (SB) _) && symIsRO(sym) && is32BitInt(t) => (MOVLconst [int32(read32(sym, int64(off), config.ctxt.Arch.ByteOrder))])
1563 (MOVLload <t> [off] {sym} (SB) _) && symIsRO(sym) && is64BitInt(t) => (MOVQconst [int64(read32(sym, int64(off), config.ctxt.Arch.ByteOrder))])
1564 (MOVQload [off] {sym} (SB) _) && symIsRO(sym) => (MOVQconst [int64(read64(sym, int64(off), config.ctxt.Arch.ByteOrder))])
1565 (MOVBQSXload [off] {sym} (SB) _) && symIsRO(sym) => (MOVQconst [int64(int8(read8(sym, int64(off))))])
1566 (MOVWQSXload [off] {sym} (SB) _) && symIsRO(sym) => (MOVQconst [int64(int16(read16(sym, int64(off), config.ctxt.Arch.ByteOrder)))])
1567 (MOVLQSXload [off] {sym} (SB) _) && symIsRO(sym) => (MOVQconst [int64(int32(read32(sym, int64(off), config.ctxt.Arch.ByteOrder)))])
1568
1569
1570 (MOVOstore [dstOff] {dstSym} ptr (MOVOload [srcOff] {srcSym} (SB) _) mem) && symIsRO(srcSym) =>
1571 (MOVQstore [dstOff+8] {dstSym} ptr (MOVQconst [int64(read64(srcSym, int64(srcOff)+8, config.ctxt.Arch.ByteOrder))])
1572 (MOVQstore [dstOff] {dstSym} ptr (MOVQconst [int64(read64(srcSym, int64(srcOff), config.ctxt.Arch.ByteOrder))]) mem))
1573
1574 // Arch-specific inlining for small or disjoint runtime.memmove
1575 // Match post-lowering calls, memory version.
1576 (SelectN [0] call:(CALLstatic {sym} s1:(MOVQstoreconst _ [sc] s2:(MOVQstore _ src s3:(MOVQstore _ dst mem)))))
1577 && sc.Val64() >= 0
1578 && isSameCall(sym, "runtime.memmove")
1579 && s1.Uses == 1 && s2.Uses == 1 && s3.Uses == 1
1580 && isInlinableMemmove(dst, src, sc.Val64(), config)
1581 && clobber(s1, s2, s3, call)
1582 => (Move [sc.Val64()] dst src mem)
1583
1584 // Match post-lowering calls, register version.
1585 (SelectN [0] call:(CALLstatic {sym} dst src (MOVQconst [sz]) mem))
1586 && sz >= 0
1587 && isSameCall(sym, "runtime.memmove")
1588 && call.Uses == 1
1589 && isInlinableMemmove(dst, src, sz, config)
1590 && clobber(call)
1591 => (Move [sz] dst src mem)
1592
1593 // Prefetch instructions
1594 (PrefetchCache ...) => (PrefetchT0 ...)
1595 (PrefetchCacheStreamed ...) => (PrefetchNTA ...)
1596
1597 // CPUID feature: BMI1.
1598 (AND(Q|L) x (NOT(Q|L) y)) && buildcfg.GOAMD64 >= 3 => (ANDN(Q|L) x y)
1599 (AND(Q|L) x (NEG(Q|L) x)) && buildcfg.GOAMD64 >= 3 => (BLSI(Q|L) x)
1600 (XOR(Q|L) x (ADD(Q|L)const [-1] x)) && buildcfg.GOAMD64 >= 3 => (BLSMSK(Q|L) x)
1601 (AND(Q|L) <t> x (ADD(Q|L)const [-1] x)) && buildcfg.GOAMD64 >= 3 => (Select0 <t> (BLSR(Q|L) x))
1602 // eliminate TEST instruction in classical "isPowerOfTwo" check
1603 (SETEQ (TEST(Q|L) s:(Select0 blsr:(BLSR(Q|L) _)) s)) => (SETEQ (Select1 <types.TypeFlags> blsr))
1604 (CMOVQEQ x y (TEST(Q|L) s:(Select0 blsr:(BLSR(Q|L) _)) s)) => (CMOVQEQ x y (Select1 <types.TypeFlags> blsr))
1605 (CMOVLEQ x y (TEST(Q|L) s:(Select0 blsr:(BLSR(Q|L) _)) s)) => (CMOVLEQ x y (Select1 <types.TypeFlags> blsr))
1606 (EQ (TEST(Q|L) s:(Select0 blsr:(BLSR(Q|L) _)) s) yes no) => (EQ (Select1 <types.TypeFlags> blsr) yes no)
1607 (SETNE (TEST(Q|L) s:(Select0 blsr:(BLSR(Q|L) _)) s)) => (SETNE (Select1 <types.TypeFlags> blsr))
1608 (CMOVQNE x y (TEST(Q|L) s:(Select0 blsr:(BLSR(Q|L) _)) s)) => (CMOVQNE x y (Select1 <types.TypeFlags> blsr))
1609 (CMOVLNE x y (TEST(Q|L) s:(Select0 blsr:(BLSR(Q|L) _)) s)) => (CMOVLNE x y (Select1 <types.TypeFlags> blsr))
1610 (NE (TEST(Q|L) s:(Select0 blsr:(BLSR(Q|L) _)) s) yes no) => (NE (Select1 <types.TypeFlags> blsr) yes no)
1611
1612 (BSWAP(Q|L) (BSWAP(Q|L) p)) => p
1613
1614 // CPUID feature: MOVBE.
1615 (MOV(Q|L)store [i] {s} p x:(BSWAP(Q|L) w) mem) && x.Uses == 1 && buildcfg.GOAMD64 >= 3 => (MOVBE(Q|L)store [i] {s} p w mem)
1616 (MOVBE(Q|L)store [i] {s} p x:(BSWAP(Q|L) w) mem) && x.Uses == 1 => (MOV(Q|L)store [i] {s} p w mem)
1617 (BSWAP(Q|L) x:(MOV(Q|L)load [i] {s} p mem)) && x.Uses == 1 && buildcfg.GOAMD64 >= 3 => @x.Block (MOVBE(Q|L)load [i] {s} p mem)
1618 (BSWAP(Q|L) x:(MOVBE(Q|L)load [i] {s} p mem)) && x.Uses == 1 => @x.Block (MOV(Q|L)load [i] {s} p mem)
1619 (MOVWstore [i] {s} p x:(ROLWconst [8] w) mem) && x.Uses == 1 && buildcfg.GOAMD64 >= 3 => (MOVBEWstore [i] {s} p w mem)
1620 (MOVBEWstore [i] {s} p x:(ROLWconst [8] w) mem) && x.Uses == 1 => (MOVWstore [i] {s} p w mem)
1621
1622 (SAR(Q|L) l:(MOV(Q|L)load [off] {sym} ptr mem) x) && buildcfg.GOAMD64 >= 3 && canMergeLoad(v, l) && clobber(l) => (SARX(Q|L)load [off] {sym} ptr x mem)
1623 (SHL(Q|L) l:(MOV(Q|L)load [off] {sym} ptr mem) x) && buildcfg.GOAMD64 >= 3 && canMergeLoad(v, l) && clobber(l) => (SHLX(Q|L)load [off] {sym} ptr x mem)
1624 (SHR(Q|L) l:(MOV(Q|L)load [off] {sym} ptr mem) x) && buildcfg.GOAMD64 >= 3 && canMergeLoad(v, l) && clobber(l) => (SHRX(Q|L)load [off] {sym} ptr x mem)
1625
1626 ((SHL|SHR|SAR)XQload [off] {sym} ptr (MOVQconst [c]) mem) => ((SHL|SHR|SAR)Qconst [int8(c&63)] (MOVQload [off] {sym} ptr mem))
1627 ((SHL|SHR|SAR)XQload [off] {sym} ptr (MOVLconst [c]) mem) => ((SHL|SHR|SAR)Qconst [int8(c&63)] (MOVQload [off] {sym} ptr mem))
1628 ((SHL|SHR|SAR)XLload [off] {sym} ptr (MOVLconst [c]) mem) => ((SHL|SHR|SAR)Lconst [int8(c&31)] (MOVLload [off] {sym} ptr mem))
1629
1630 // Convert atomic logical operations to easier ones if we don't use the result.
1631 (Select1 a:(LoweredAtomic(And64|And32|Or64|Or32) ptr val mem)) && a.Uses == 1 && clobber(a) => ((ANDQ|ANDL|ORQ|ORL)lock ptr val mem)
1632
1633 // If we are checking the results of an add, use the flags directly from the add.
1634 // Note that this only works for EQ/NE. ADD sets the CF/OF flags differently
1635 // than TEST sets them.
1636 // Note also that a.Args[0] here refers to the post-flagify'd value.
1637 ((EQ|NE) t:(TESTQ a:(ADDQconst [c] x) a)) && t.Uses == 1 && flagify(a) => ((EQ|NE) (Select1 <types.TypeFlags> a.Args[0]))
1638 ((EQ|NE) t:(TESTL a:(ADDLconst [c] x) a)) && t.Uses == 1 && flagify(a) => ((EQ|NE) (Select1 <types.TypeFlags> a.Args[0]))
1639
1640 // If we don't use the flags any more, just use the standard op.
1641 (Select0 a:(ADD(Q|L)constflags [c] x)) && a.Uses == 1 => (ADD(Q|L)const [c] x)
1642
1643 // SIMD lowering rules
1644
1645 // Mask conversions
1646 // integers to masks
1647 (Cvt16toMask8x16 <t> x) => (VPMOVMToVec8x16 <types.TypeVec128> (KMOVWk <t> x))
1648 (Cvt32toMask8x32 <t> x) => (VPMOVMToVec8x32 <types.TypeVec256> (KMOVDk <t> x))
1649 (Cvt64toMask8x64 <t> x) => (VPMOVMToVec8x64 <types.TypeVec512> (KMOVQk <t> x))
1650
1651 (Cvt8toMask16x8 <t> x) => (VPMOVMToVec16x8 <types.TypeVec128> (KMOVBk <t> x))
1652 (Cvt16toMask16x16 <t> x) => (VPMOVMToVec16x16 <types.TypeVec256> (KMOVWk <t> x))
1653 (Cvt32toMask16x32 <t> x) => (VPMOVMToVec16x32 <types.TypeVec512> (KMOVDk <t> x))
1654
1655 (Cvt8toMask32x4 <t> x) => (VPMOVMToVec32x4 <types.TypeVec128> (KMOVBk <t> x))
1656 (Cvt8toMask32x8 <t> x) => (VPMOVMToVec32x8 <types.TypeVec256> (KMOVBk <t> x))
1657 (Cvt16toMask32x16 <t> x) => (VPMOVMToVec32x16 <types.TypeVec512> (KMOVWk <t> x))
1658
1659 (Cvt8toMask64x2 <t> x) => (VPMOVMToVec64x2 <types.TypeVec128> (KMOVBk <t> x))
1660 (Cvt8toMask64x4 <t> x) => (VPMOVMToVec64x4 <types.TypeVec256> (KMOVBk <t> x))
1661 (Cvt8toMask64x8 <t> x) => (VPMOVMToVec64x8 <types.TypeVec512> (KMOVBk <t> x))
1662
1663 // masks to integers
1664 (CvtMask8x16to16 ...) => (VPMOVMSKB128 ...)
1665 (CvtMask8x32to32 ...) => (VPMOVMSKB256 ...)
1666 (CvtMask8x64to64 x) => (KMOVQi (VPMOVVec8x64ToM <types.TypeMask> x))
1667
1668 (CvtMask16x8to8 x) => (KMOVBi (VPMOVVec16x8ToM <types.TypeMask> x))
1669 (CvtMask16x16to16 x) => (KMOVWi (VPMOVVec16x16ToM <types.TypeMask> x))
1670 (CvtMask16x32to32 x) => (KMOVDi (VPMOVVec16x32ToM <types.TypeMask> x))
1671
1672 (CvtMask32x4to8 ...) => (VMOVMSKPS128 ...)
1673 (CvtMask32x8to8 ...) => (VMOVMSKPS256 ...)
1674 (CvtMask32x16to16 x) => (KMOVWi (VPMOVVec32x16ToM <types.TypeMask> x))
1675
1676 (CvtMask64x2to8 ...) => (VMOVMSKPD128 ...)
1677 (CvtMask64x4to8 ...) => (VMOVMSKPD256 ...)
1678 (CvtMask64x8to8 x) => (KMOVBi (VPMOVVec64x8ToM <types.TypeMask> x))
1679
1680 // optimizations
1681 (MOVBstore [off] {sym} ptr (KMOVBi mask) mem) => (KMOVBstore [off] {sym} ptr mask mem)
1682 (MOVWstore [off] {sym} ptr (KMOVWi mask) mem) => (KMOVWstore [off] {sym} ptr mask mem)
1683 (MOVLstore [off] {sym} ptr (KMOVDi mask) mem) => (KMOVDstore [off] {sym} ptr mask mem)
1684 (MOVQstore [off] {sym} ptr (KMOVQi mask) mem) => (KMOVQstore [off] {sym} ptr mask mem)
1685
1686 (KMOVBk l:(MOVBload [off] {sym} ptr mem)) && canMergeLoad(v, l) && clobber(l) => (KMOVBload [off] {sym} ptr mem)
1687 (KMOVWk l:(MOVWload [off] {sym} ptr mem)) && canMergeLoad(v, l) && clobber(l) => (KMOVWload [off] {sym} ptr mem)
1688 (KMOVDk l:(MOVLload [off] {sym} ptr mem)) && canMergeLoad(v, l) && clobber(l) => (KMOVDload [off] {sym} ptr mem)
1689 (KMOVQk l:(MOVQload [off] {sym} ptr mem)) && canMergeLoad(v, l) && clobber(l) => (KMOVQload [off] {sym} ptr mem)
1690
1691 // SIMD vector loads and stores
1692 (Load <t> ptr mem) && t.Size() == 16 => (VMOVDQUload128 ptr mem)
1693 (Store {t} ptr val mem) && t.Size() == 16 => (VMOVDQUstore128 ptr val mem)
1694
1695 (Load <t> ptr mem) && t.Size() == 32 => (VMOVDQUload256 ptr mem)
1696 (Store {t} ptr val mem) && t.Size() == 32 => (VMOVDQUstore256 ptr val mem)
1697
1698 (Load <t> ptr mem) && t.Size() == 64 => (VMOVDQUload512 ptr mem)
1699 (Store {t} ptr val mem) && t.Size() == 64 => (VMOVDQUstore512 ptr val mem)
1700
1701 // SIMD vector integer-vector-masked loads and stores.
1702 (LoadMasked32 <t> ptr mask mem) && t.Size() == 16 => (VPMASK32load128 ptr mask mem)
1703 (LoadMasked32 <t> ptr mask mem) && t.Size() == 32 => (VPMASK32load256 ptr mask mem)
1704 (LoadMasked64 <t> ptr mask mem) && t.Size() == 16 => (VPMASK64load128 ptr mask mem)
1705 (LoadMasked64 <t> ptr mask mem) && t.Size() == 32 => (VPMASK64load256 ptr mask mem)
1706
1707 (StoreMasked32 {t} ptr mask val mem) && t.Size() == 16 => (VPMASK32store128 ptr mask val mem)
1708 (StoreMasked32 {t} ptr mask val mem) && t.Size() == 32 => (VPMASK32store256 ptr mask val mem)
1709 (StoreMasked64 {t} ptr mask val mem) && t.Size() == 16 => (VPMASK64store128 ptr mask val mem)
1710 (StoreMasked64 {t} ptr mask val mem) && t.Size() == 32 => (VPMASK64store256 ptr mask val mem)
1711
1712 // Misc
1713 (IsZeroVec x) => (SETEQ (VPTEST x x))
1714
1715 (IsNaNFloat32x4 x) => (VCMPPS128 [3] x x)
1716 (IsNaNFloat32x8 x) => (VCMPPS256 [3] x x)
1717 (IsNaNFloat32x16 x) => (VPMOVMToVec32x16 (VCMPPS512 [3] x x))
1718 (IsNaNFloat64x2 x) => (VCMPPD128 [3] x x)
1719 (IsNaNFloat64x4 x) => (VCMPPD256 [3] x x)
1720 (IsNaNFloat64x8 x) => (VPMOVMToVec64x8 (VCMPPD512 [3] x x))
1721
1722 // SIMD vector K-masked loads and stores
1723
1724 (LoadMasked64 <t> ptr mask mem) && t.Size() == 64 => (VPMASK64load512 ptr (VPMOVVec64x8ToM <types.TypeMask> mask) mem)
1725 (LoadMasked32 <t> ptr mask mem) && t.Size() == 64 => (VPMASK32load512 ptr (VPMOVVec32x16ToM <types.TypeMask> mask) mem)
1726 (LoadMasked16 <t> ptr mask mem) && t.Size() == 64 => (VPMASK16load512 ptr (VPMOVVec16x32ToM <types.TypeMask> mask) mem)
1727 (LoadMasked8 <t> ptr mask mem) && t.Size() == 64 => (VPMASK8load512 ptr (VPMOVVec8x64ToM <types.TypeMask> mask) mem)
1728
1729 (StoreMasked64 {t} ptr mask val mem) && t.Size() == 64 => (VPMASK64store512 ptr (VPMOVVec64x8ToM <types.TypeMask> mask) val mem)
1730 (StoreMasked32 {t} ptr mask val mem) && t.Size() == 64 => (VPMASK32store512 ptr (VPMOVVec32x16ToM <types.TypeMask> mask) val mem)
1731 (StoreMasked16 {t} ptr mask val mem) && t.Size() == 64 => (VPMASK16store512 ptr (VPMOVVec16x32ToM <types.TypeMask> mask) val mem)
1732 (StoreMasked8 {t} ptr mask val mem) && t.Size() == 64 => (VPMASK8store512 ptr (VPMOVVec8x64ToM <types.TypeMask> mask) val mem)
1733
1734 (ZeroSIMD <t>) && t.Size() == 16 => (Zero128 <t>)
1735 (ZeroSIMD <t>) && t.Size() == 32 => (Zero256 <t>)
1736 (ZeroSIMD <t>) && t.Size() == 64 => (Zero512 <t>)
1737
1738 // optimize x.IsNaN().Or(y.IsNaN())
1739 // do these before the mask rewrites
1740 (VPOR128 (VCMPP(S|D)128 [3] x x) (VCMPP(S|D)128 [3] y y)) => (VCMPP(S|D)128 [3] x y)
1741 (VPOR256 (VCMPP(S|D)256 [3] x x) (VCMPP(S|D)256 [3] y y)) => (VCMPP(S|D)256 [3] x y)
1742 (VPORD512 (VPMOVMToVec32x16 (VCMPPS512 [3] x x)) (VPMOVMToVec32x16 (VCMPPS512 [3] y y))) =>
1743 (VPMOVMToVec32x16 (VCMPPS512 [3] x y))
1744 (VPORD512 (VPMOVMToVec64x8 (VCMPPD512 [3] x x)) (VPMOVMToVec64x8 (VCMPPD512 [3] y y))) =>
1745 (VPMOVMToVec64x8 (VCMPPD512 [3] x y))
1746
1747 // Include these rules because you never know about rewrite order
1748 (KANDB (VCMPPD512 [3] x x) (VCMPPD512 [3] y y)) => (VCMPPD512 [3] x x) // 512 = 64x8 -> KANDB
1749 (KANDW (VCMPPS512 [3] x x) (VCMPPS512 [3] y y)) => (VCMPPS512 [3] x y) // 512 = 32x16 -> KANDW
1750
1751 // These larger simplifying rules must come before the smaller simplifying rules that might break them).
1752 // Rewrite rules for binary logical mask operations that apply to 8-bit elements (B, for bytes) of 128, 256, and 512-bit vectors
1753 (VPAND128 (VPMOVMToVec8x16 x) (VPMOVMToVec8x16 y)) && v.Block.CPUfeatures.hasFeature(CPUavx512) => (VPMOVMToVec8x16 (KANDW x y))
1754 (VPAND256 (VPMOVMToVec8x32 x) (VPMOVMToVec8x32 y)) && v.Block.CPUfeatures.hasFeature(CPUavx512) => (VPMOVMToVec8x32 (KANDD x y))
1755 (VPANDD512 (VPMOVMToVec8x64 x) (VPMOVMToVec8x64 y)) && v.Block.CPUfeatures.hasFeature(CPUavx512) => (VPMOVMToVec8x64 (KANDQ x y))
1756
1757 (VPOR128 (VPMOVMToVec8x16 x) (VPMOVMToVec8x16 y)) && v.Block.CPUfeatures.hasFeature(CPUavx512) => (VPMOVMToVec8x16 (KORW x y))
1758 (VPOR256 (VPMOVMToVec8x32 x) (VPMOVMToVec8x32 y)) && v.Block.CPUfeatures.hasFeature(CPUavx512) => (VPMOVMToVec8x32 (KORD x y))
1759 (VPORD512 (VPMOVMToVec8x64 x) (VPMOVMToVec8x64 y)) && v.Block.CPUfeatures.hasFeature(CPUavx512) => (VPMOVMToVec8x64 (KORQ x y))
1760
1761 (VPXOR128 (VPMOVMToVec8x16 x) (VPMOVMToVec8x16 y)) && v.Block.CPUfeatures.hasFeature(CPUavx512) => (VPMOVMToVec8x16 (KXORW x y))
1762 (VPXOR256 (VPMOVMToVec8x32 x) (VPMOVMToVec8x32 y)) && v.Block.CPUfeatures.hasFeature(CPUavx512) => (VPMOVMToVec8x32 (KXORD x y))
1763 (VPXORD512 (VPMOVMToVec8x64 x) (VPMOVMToVec8x64 y)) && v.Block.CPUfeatures.hasFeature(CPUavx512) => (VPMOVMToVec8x64 (KXORQ x y))
1764
1765 // Rewrite rules for binary logical mask operations that apply to 16-bit elements (W, for words) of 128, 256, and 512-bit vectors
1766 (VPAND128 (VPMOVMToVec16x8 x) (VPMOVMToVec16x8 y)) && v.Block.CPUfeatures.hasFeature(CPUavx512) => (VPMOVMToVec16x8 (KANDB x y))
1767 (VPAND256 (VPMOVMToVec16x16 x) (VPMOVMToVec16x16 y)) && v.Block.CPUfeatures.hasFeature(CPUavx512) => (VPMOVMToVec16x16 (KANDW x y))
1768 (VPANDD512 (VPMOVMToVec16x32 x) (VPMOVMToVec16x32 y)) && v.Block.CPUfeatures.hasFeature(CPUavx512) => (VPMOVMToVec16x32 (KANDD x y))
1769
1770 (VPOR128 (VPMOVMToVec16x8 x) (VPMOVMToVec16x8 y)) && v.Block.CPUfeatures.hasFeature(CPUavx512) => (VPMOVMToVec16x8 (KORB x y))
1771 (VPOR256 (VPMOVMToVec16x16 x) (VPMOVMToVec16x16 y)) && v.Block.CPUfeatures.hasFeature(CPUavx512) => (VPMOVMToVec16x16 (KORW x y))
1772 (VPORD512 (VPMOVMToVec16x32 x) (VPMOVMToVec16x32 y)) && v.Block.CPUfeatures.hasFeature(CPUavx512) => (VPMOVMToVec16x32 (KORD x y))
1773
1774 (VPXOR128 (VPMOVMToVec16x8 x) (VPMOVMToVec16x8 y)) && v.Block.CPUfeatures.hasFeature(CPUavx512) => (VPMOVMToVec16x8 (KXORB x y))
1775 (VPXOR256 (VPMOVMToVec16x16 x) (VPMOVMToVec16x16 y)) && v.Block.CPUfeatures.hasFeature(CPUavx512) => (VPMOVMToVec16x16 (KXORW x y))
1776 (VPXORD512 (VPMOVMToVec16x32 x) (VPMOVMToVec16x32 y)) && v.Block.CPUfeatures.hasFeature(CPUavx512) => (VPMOVMToVec16x32 (KXORD x y))
1777
1778 // Rewrite rules for binary logical mask operations that apply to 32-bit elements (D, for doublewords) of 128, 256, and 512-bit vectors
1779 (VPAND128 (VPMOVMToVec32x4 x) (VPMOVMToVec32x4 y)) && v.Block.CPUfeatures.hasFeature(CPUavx512) => (VPMOVMToVec32x4 (KANDB x y))
1780 (VPAND256 (VPMOVMToVec32x8 x) (VPMOVMToVec32x8 y)) && v.Block.CPUfeatures.hasFeature(CPUavx512) => (VPMOVMToVec32x8 (KANDB x y))
1781 (VPANDD512 (VPMOVMToVec32x16 x) (VPMOVMToVec32x16 y)) && v.Block.CPUfeatures.hasFeature(CPUavx512) => (VPMOVMToVec32x16 (KANDW x y))
1782
1783 (VPOR128 (VPMOVMToVec32x4 x) (VPMOVMToVec32x4 y)) && v.Block.CPUfeatures.hasFeature(CPUavx512) => (VPMOVMToVec32x4 (KORB x y))
1784 (VPOR256 (VPMOVMToVec32x8 x) (VPMOVMToVec32x8 y)) && v.Block.CPUfeatures.hasFeature(CPUavx512) => (VPMOVMToVec32x8 (KORB x y))
1785 (VPORD512 (VPMOVMToVec32x16 x) (VPMOVMToVec32x16 y)) && v.Block.CPUfeatures.hasFeature(CPUavx512) => (VPMOVMToVec32x16 (KORW x y))
1786
1787 (VPXOR128 (VPMOVMToVec32x4 x) (VPMOVMToVec32x4 y)) && v.Block.CPUfeatures.hasFeature(CPUavx512) => (VPMOVMToVec32x4 (KXORB x y))
1788 (VPXOR256 (VPMOVMToVec32x8 x) (VPMOVMToVec32x8 y)) && v.Block.CPUfeatures.hasFeature(CPUavx512) => (VPMOVMToVec32x8 (KXORB x y))
1789 (VPXORD512 (VPMOVMToVec32x16 x) (VPMOVMToVec32x16 y)) && v.Block.CPUfeatures.hasFeature(CPUavx512) => (VPMOVMToVec32x16 (KXORW x y))
1790
1791 // Rewrite rules for binary logical mask operations that apply to 64-bit elements (Q, for quadwords) of 128, 256, and 512-bit vectors
1792 (VPAND128 (VPMOVMToVec64x2 x) (VPMOVMToVec64x2 y)) && v.Block.CPUfeatures.hasFeature(CPUavx512) => (VPMOVMToVec64x2 (KANDB x y))
1793 (VPAND256 (VPMOVMToVec64x4 x) (VPMOVMToVec64x4 y)) && v.Block.CPUfeatures.hasFeature(CPUavx512) => (VPMOVMToVec64x4 (KANDB x y))
1794 (VPANDD512 (VPMOVMToVec64x8 x) (VPMOVMToVec64x8 y)) && v.Block.CPUfeatures.hasFeature(CPUavx512) => (VPMOVMToVec64x8 (KANDB x y))
1795
1796 (VPOR128 (VPMOVMToVec64x2 x) (VPMOVMToVec64x2 y)) && v.Block.CPUfeatures.hasFeature(CPUavx512) => (VPMOVMToVec64x2 (KORB x y))
1797 (VPOR256 (VPMOVMToVec64x4 x) (VPMOVMToVec64x4 y)) && v.Block.CPUfeatures.hasFeature(CPUavx512) => (VPMOVMToVec64x4 (KORB x y))
1798 (VPORD512 (VPMOVMToVec64x8 x) (VPMOVMToVec64x8 y)) && v.Block.CPUfeatures.hasFeature(CPUavx512) => (VPMOVMToVec64x8 (KORB x y))
1799
1800 (VPXOR128 (VPMOVMToVec64x2 x) (VPMOVMToVec64x2 y)) && v.Block.CPUfeatures.hasFeature(CPUavx512) => (VPMOVMToVec64x2 (KXORB x y))
1801 (VPXOR256 (VPMOVMToVec64x4 x) (VPMOVMToVec64x4 y)) && v.Block.CPUfeatures.hasFeature(CPUavx512) => (VPMOVMToVec64x4 (KXORB x y))
1802 (VPXORD512 (VPMOVMToVec64x8 x) (VPMOVMToVec64x8 y)) && v.Block.CPUfeatures.hasFeature(CPUavx512) => (VPMOVMToVec64x8 (KXORB x y))
1803
1804 (VPMOVVec8x16ToM (VPMOVMToVec8x16 x)) => x
1805 (VPMOVVec8x32ToM (VPMOVMToVec8x32 x)) => x
1806 (VPMOVVec8x64ToM (VPMOVMToVec8x64 x)) => x
1807
1808 (VPMOVVec16x8ToM (VPMOVMToVec16x8 x)) => x
1809 (VPMOVVec16x16ToM (VPMOVMToVec16x16 x)) => x
1810 (VPMOVVec16x32ToM (VPMOVMToVec16x32 x)) => x
1811
1812 (VPMOVVec32x4ToM (VPMOVMToVec32x4 x)) => x
1813 (VPMOVVec32x8ToM (VPMOVMToVec32x8 x)) => x
1814 (VPMOVVec32x16ToM (VPMOVMToVec32x16 x)) => x
1815
1816 (VPMOVVec64x2ToM (VPMOVMToVec64x2 x)) => x
1817 (VPMOVVec64x4ToM (VPMOVMToVec64x4 x)) => x
1818 (VPMOVVec64x8ToM (VPMOVMToVec64x8 x)) => x
1819
1820 (VPANDQ512 x (VPMOVMToVec64x8 k)) => (VMOVDQU64Masked512 x k)
1821 (VPANDQ512 x (VPMOVMToVec32x16 k)) => (VMOVDQU32Masked512 x k)
1822 (VPANDQ512 x (VPMOVMToVec16x32 k)) => (VMOVDQU16Masked512 x k)
1823 (VPANDQ512 x (VPMOVMToVec8x64 k)) => (VMOVDQU8Masked512 x k)
1824 (VPANDD512 x (VPMOVMToVec64x8 k)) => (VMOVDQU64Masked512 x k)
1825 (VPANDD512 x (VPMOVMToVec32x16 k)) => (VMOVDQU32Masked512 x k)
1826 (VPANDD512 x (VPMOVMToVec16x32 k)) => (VMOVDQU16Masked512 x k)
1827 (VPANDD512 x (VPMOVMToVec8x64 k)) => (VMOVDQU8Masked512 x k)
1828
1829 (VPAND128 x (VPMOVMToVec8x16 k)) && v.Block.CPUfeatures.hasFeature(CPUavx512) => (VMOVDQU8Masked128 x k)
1830 (VPAND128 x (VPMOVMToVec16x8 k)) && v.Block.CPUfeatures.hasFeature(CPUavx512) => (VMOVDQU16Masked128 x k)
1831 (VPAND128 x (VPMOVMToVec32x4 k)) && v.Block.CPUfeatures.hasFeature(CPUavx512) => (VMOVDQU32Masked128 x k)
1832 (VPAND128 x (VPMOVMToVec64x2 k)) && v.Block.CPUfeatures.hasFeature(CPUavx512) => (VMOVDQU64Masked128 x k)
1833
1834 (VPAND256 x (VPMOVMToVec8x32 k)) && v.Block.CPUfeatures.hasFeature(CPUavx512) => (VMOVDQU8Masked256 x k)
1835 (VPAND256 x (VPMOVMToVec16x16 k)) && v.Block.CPUfeatures.hasFeature(CPUavx512) => (VMOVDQU16Masked256 x k)
1836 (VPAND256 x (VPMOVMToVec32x8 k)) && v.Block.CPUfeatures.hasFeature(CPUavx512) => (VMOVDQU32Masked256 x k)
1837 (VPAND256 x (VPMOVMToVec64x4 k)) && v.Block.CPUfeatures.hasFeature(CPUavx512) => (VMOVDQU64Masked256 x k)
1838
1839 // Insert to zero of 32/64 bit floats and ints to a zero is just MOVS[SD]
1840 (VPINSRQ128 [0] (Zero128 <t>) y) && y.Type.IsFloat() => (VMOVSDf2v <types.TypeVec128> y)
1841 (VPINSRD128 [0] (Zero128 <t>) y) && y.Type.IsFloat() => (VMOVSSf2v <types.TypeVec128> y)
1842 (VPINSRQ128 [0] (Zero128 <t>) y) && !y.Type.IsFloat() => (VMOVQ <types.TypeVec128> y)
1843 (VPINSRD128 [0] (Zero128 <t>) y) && !y.Type.IsFloat() => (VMOVD <types.TypeVec128> y)
1844
1845 // These rewrites can skip zero-extending the 8/16-bit inputs because they are
1846 // only used as the input to a broadcast; the potentially "bad" bits are ignored
1847 (VPBROADCASTB(128|256|512) x:(VPINSRB128 [0] (Zero128 <t>) y)) && x.Uses == 1 =>
1848 (VPBROADCASTB(128|256|512) (VMOVQ <types.TypeVec128> y))
1849 (VPBROADCASTW(128|256|512) x:(VPINSRW128 [0] (Zero128 <t>) y)) && x.Uses == 1 =>
1850 (VPBROADCASTW(128|256|512) (VMOVQ <types.TypeVec128> y))
1851
1852 (VMOVQ x:(MOVQload [off] {sym} ptr mem)) && x.Uses == 1 && clobber(x) => @x.Block (VMOVQload <v.Type> [off] {sym} ptr mem)
1853 (VMOVD x:(MOVLload [off] {sym} ptr mem)) && x.Uses == 1 && clobber(x) => @x.Block (VMOVDload <v.Type> [off] {sym} ptr mem)
1854
1855 (VMOVSDf2v x:(MOVSDload [off] {sym} ptr mem)) && x.Uses == 1 && clobber(x) => @x.Block (VMOVSDload <v.Type> [off] {sym} ptr mem)
1856 (VMOVSSf2v x:(MOVSSload [off] {sym} ptr mem)) && x.Uses == 1 && clobber(x) => @x.Block (VMOVSSload <v.Type> [off] {sym} ptr mem)
1857
1858 (VMOVSDf2v x:(MOVSDconst [c] )) => (VMOVSDconst [c] )
1859 (VMOVSSf2v x:(MOVSSconst [c] )) => (VMOVSSconst [c] )
1860
1861 (VMOVDQUload(128|256|512) [off1] {sym} x:(ADDQconst [off2] ptr) mem) && is32Bit(int64(off1)+int64(off2)) => (VMOVDQUload(128|256|512) [off1+off2] {sym} ptr mem)
1862 (VMOVDQUstore(128|256|512) [off1] {sym} x:(ADDQconst [off2] ptr) val mem) && is32Bit(int64(off1)+int64(off2)) => (VMOVDQUstore(128|256|512) [off1+off2] {sym} ptr val mem)
1863 (VMOVDQUload(128|256|512) [off1] {sym1} x:(LEAQ [off2] {sym2} base) mem) && is32Bit(int64(off1)+int64(off2)) && canMergeSym(sym1, sym2) => (VMOVDQUload(128|256|512) [off1+off2] {mergeSym(sym1, sym2)} base mem)
1864 (VMOVDQUstore(128|256|512) [off1] {sym1} x:(LEAQ [off2] {sym2} base) val mem) && is32Bit(int64(off1)+int64(off2)) && canMergeSym(sym1, sym2) => (VMOVDQUstore(128|256|512) [off1+off2] {mergeSym(sym1, sym2)} base val mem)
1865
1866 // 2-op VPTEST optimizations
1867 (SETEQ (VPTEST x:(VPAND(128|256) j k) y)) && x == y && x.Uses == 2 => (SETEQ (VPTEST j k))
1868 (SETEQ (VPTEST x:(VPAND(D|Q)512 j k) y)) && x == y && x.Uses == 2 => (SETEQ (VPTEST j k))
1869 (SETEQ (VPTEST x:(VPANDN(128|256) j k) y)) && x == y && x.Uses == 2 => (SETB (VPTEST k j)) // AndNot has swapped its operand order
1870 (SETEQ (VPTEST x:(VPANDN(D|Q)512 j k) y)) && x == y && x.Uses == 2 => (SETB (VPTEST k j)) // AndNot has swapped its operand order
1871 (EQ (VPTEST x:(VPAND(128|256) j k) y) yes no) && x == y && x.Uses == 2 => (EQ (VPTEST j k) yes no)
1872 (EQ (VPTEST x:(VPAND(D|Q)512 j k) y) yes no) && x == y && x.Uses == 2 => (EQ (VPTEST j k) yes no)
1873 (EQ (VPTEST x:(VPANDN(128|256) j k) y) yes no) && x == y && x.Uses == 2 => (ULT (VPTEST k j) yes no) // AndNot has swapped its operand order
1874 (EQ (VPTEST x:(VPANDN(D|Q)512 j k) y) yes no) && x == y && x.Uses == 2 => (ULT (VPTEST k j) yes no) // AndNot has swapped its operand order
1875
1876 // remove flags → bool → flags roundtrip
1877 // Only do it if the flag generating instruction is local otherwise the likelihood flagalloc won't undo this optimization and makes things worse are slim.
1878 (NE t:(TESTQ x:(MOVBQZX s:(SET(EQ|NE|L|G|LE|GE|A|B|AE|BE|EQF|NEF|GF|GEF) flags)) x) yes no) && t.Block == s.Block => ((EQ|NE|LT|GT|LE|GE|UGT|ULT|UGE|ULE|EQF|NEF|UGT|UGE) flags yes no)
1879 (NE t:(TESTL x:(MOVBQZX s:(SET(EQ|NE|L|G|LE|GE|A|B|AE|BE|EQF|NEF|GF|GEF) flags)) x) yes no) && t.Block == s.Block => ((EQ|NE|LT|GT|LE|GE|UGT|ULT|UGE|ULE|EQF|NEF|UGT|UGE) flags yes no)
1880 (NE t:(TESTW x:(MOVBQZX s:(SET(EQ|NE|L|G|LE|GE|A|B|AE|BE|EQF|NEF|GF|GEF) flags)) x) yes no) && t.Block == s.Block => ((EQ|NE|LT|GT|LE|GE|UGT|ULT|UGE|ULE|EQF|NEF|UGT|UGE) flags yes no)
1881 (NE t:(TESTB s:(SET(EQ|NE|L|G|LE|GE|A|B|AE|BE|EQF|NEF|GF|GEF) flags) s) yes no) && t.Block == s.Block => ((EQ|NE|LT|GT|LE|GE|UGT|ULT|UGE|ULE|EQF|NEF|UGT|UGE) flags yes no)
1882
1883 (CMOVQNE yes no t:(TESTQ x:(MOVBQZX s:(SET(EQ|NE|L|G|LE|GE|A|B|AE|BE|EQF|NEF|GF|GEF) flags)) x)) && t.Block == s.Block => (CMOVQ(EQ|NE|LT|GT|LE|GE|HI|CS|CC|LS|EQF|NEF|GTF|GEF) yes no flags)
1884 (CMOVQNE yes no t:(TESTL x:(MOVBQZX s:(SET(EQ|NE|L|G|LE|GE|A|B|AE|BE|EQF|NEF|GF|GEF) flags)) x)) && t.Block == s.Block => (CMOVQ(EQ|NE|LT|GT|LE|GE|HI|CS|CC|LS|EQF|NEF|GTF|GEF) yes no flags)
1885 (CMOVQNE yes no t:(TESTW x:(MOVBQZX s:(SET(EQ|NE|L|G|LE|GE|A|B|AE|BE|EQF|NEF|GF|GEF) flags)) x)) && t.Block == s.Block => (CMOVQ(EQ|NE|LT|GT|LE|GE|HI|CS|CC|LS|EQF|NEF|GTF|GEF) yes no flags)
1886 (CMOVQNE yes no t:(TESTB s:(SET(EQ|NE|L|G|LE|GE|A|B|AE|BE|EQF|NEF|GF|GEF) flags) s)) && t.Block == s.Block => (CMOVQ(EQ|NE|LT|GT|LE|GE|HI|CS|CC|LS|EQF|NEF|GTF|GEF) yes no flags)
1887
1888 (CMOVLNE yes no t:(TESTQ x:(MOVBQZX s:(SET(EQ|NE|L|G|LE|GE|A|B|AE|BE|EQF|NEF|GF|GEF) flags)) x)) && t.Block == s.Block => (CMOVL(EQ|NE|LT|GT|LE|GE|HI|CS|CC|LS|EQF|NEF|GTF|GEF) yes no flags)
1889 (CMOVLNE yes no t:(TESTL x:(MOVBQZX s:(SET(EQ|NE|L|G|LE|GE|A|B|AE|BE|EQF|NEF|GF|GEF) flags)) x)) && t.Block == s.Block => (CMOVL(EQ|NE|LT|GT|LE|GE|HI|CS|CC|LS|EQF|NEF|GTF|GEF) yes no flags)
1890 (CMOVLNE yes no t:(TESTW x:(MOVBQZX s:(SET(EQ|NE|L|G|LE|GE|A|B|AE|BE|EQF|NEF|GF|GEF) flags)) x)) && t.Block == s.Block => (CMOVL(EQ|NE|LT|GT|LE|GE|HI|CS|CC|LS|EQF|NEF|GTF|GEF) yes no flags)
1891 (CMOVLNE yes no t:(TESTB s:(SET(EQ|NE|L|G|LE|GE|A|B|AE|BE|EQF|NEF|GF|GEF) flags) s)) && t.Block == s.Block => (CMOVL(EQ|NE|LT|GT|LE|GE|HI|CS|CC|LS|EQF|NEF|GTF|GEF) yes no flags)
1892
1893 (CMOVWNE yes no t:(TESTQ x:(MOVBQZX s:(SET(EQ|NE|L|G|LE|GE|A|B|AE|BE|EQF|NEF|GF|GEF) flags)) x)) && t.Block == s.Block => (CMOVW(EQ|NE|LT|GT|LE|GE|HI|CS|CC|LS|EQF|NEF|GTF|GEF) yes no flags)
1894 (CMOVWNE yes no t:(TESTL x:(MOVBQZX s:(SET(EQ|NE|L|G|LE|GE|A|B|AE|BE|EQF|NEF|GF|GEF) flags)) x)) && t.Block == s.Block => (CMOVW(EQ|NE|LT|GT|LE|GE|HI|CS|CC|LS|EQF|NEF|GTF|GEF) yes no flags)
1895 (CMOVWNE yes no t:(TESTW x:(MOVBQZX s:(SET(EQ|NE|L|G|LE|GE|A|B|AE|BE|EQF|NEF|GF|GEF) flags)) x)) && t.Block == s.Block => (CMOVW(EQ|NE|LT|GT|LE|GE|HI|CS|CC|LS|EQF|NEF|GTF|GEF) yes no flags)
1896 (CMOVWNE yes no t:(TESTB s:(SET(EQ|NE|L|G|LE|GE|A|B|AE|BE|EQF|NEF|GF|GEF) flags) s)) && t.Block == s.Block => (CMOVW(EQ|NE|LT|GT|LE|GE|HI|CS|CC|LS|EQF|NEF|GTF|GEF) yes no flags)
1897
1898 (SETNE t:(TESTQ x:(MOVBQZX s:(SET(EQ|NE|L|G|LE|GE|A|B|AE|BE|EQF|NEF|GF|GEF) flags)) x)) && t.Block == s.Block => s
1899 (SETNE t:(TESTL x:(MOVBQZX s:(SET(EQ|NE|L|G|LE|GE|A|B|AE|BE|EQF|NEF|GF|GEF) flags)) x)) && t.Block == s.Block => s
1900 (SETNE t:(TESTW x:(MOVBQZX s:(SET(EQ|NE|L|G|LE|GE|A|B|AE|BE|EQF|NEF|GF|GEF) flags)) x)) && t.Block == s.Block => s
1901 (SETNE t:(TESTB s:(SET(EQ|NE|L|G|LE|GE|A|B|AE|BE|EQF|NEF|GF|GEF) flags) s)) && t.Block == s.Block => s
1902
1903 (EQ t:(TESTQ x:(MOVBQZX s:(SET(EQ|NE|L|G|LE|GE|A|B|AE|BE) flags)) x) yes no) && t.Block == s.Block => ((NE|EQ|GE|LE|GT|LT|ULE|UGE|ULT|UGT) flags yes no)
1904 (EQ t:(TESTL x:(MOVBQZX s:(SET(EQ|NE|L|G|LE|GE|A|B|AE|BE) flags)) x) yes no) && t.Block == s.Block => ((NE|EQ|GE|LE|GT|LT|ULE|UGE|ULT|UGT) flags yes no)
1905 (EQ t:(TESTW x:(MOVBQZX s:(SET(EQ|NE|L|G|LE|GE|A|B|AE|BE) flags)) x) yes no) && t.Block == s.Block => ((NE|EQ|GE|LE|GT|LT|ULE|UGE|ULT|UGT) flags yes no)
1906 (EQ t:(TESTB s:(SET(EQ|NE|L|G|LE|GE|A|B|AE|BE) flags) s) yes no) && t.Block == s.Block => ((NE|EQ|GE|LE|GT|LT|ULE|UGE|ULT|UGT) flags yes no)
1907
1908 (CMOVQEQ yes no t:(TESTQ x:(MOVBQZX s:(SET(EQ|NE|L|G|LE|GE|A|B|AE|BE) flags)) x)) && t.Block == s.Block => (CMOVQ(NE|EQ|GE|LE|GT|LT|LS|CC|CS|HI) yes no flags)
1909 (CMOVQEQ yes no t:(TESTL x:(MOVBQZX s:(SET(EQ|NE|L|G|LE|GE|A|B|AE|BE) flags)) x)) && t.Block == s.Block => (CMOVQ(NE|EQ|GE|LE|GT|LT|LS|CC|CS|HI) yes no flags)
1910 (CMOVQEQ yes no t:(TESTW x:(MOVBQZX s:(SET(EQ|NE|L|G|LE|GE|A|B|AE|BE) flags)) x)) && t.Block == s.Block => (CMOVQ(NE|EQ|GE|LE|GT|LT|LS|CC|CS|HI) yes no flags)
1911 (CMOVQEQ yes no t:(TESTB s:(SET(EQ|NE|L|G|LE|GE|A|B|AE|BE) flags) s)) && t.Block == s.Block => (CMOVQ(NE|EQ|GE|LE|GT|LT|LS|CC|CS|HI) yes no flags)
1912
1913 (CMOVLEQ yes no t:(TESTQ x:(MOVBQZX s:(SET(EQ|NE|L|G|LE|GE|A|B|AE|BE) flags)) x)) && t.Block == s.Block => (CMOVL(NE|EQ|GE|LE|GT|LT|LS|CC|CS|HI) yes no flags)
1914 (CMOVLEQ yes no t:(TESTL x:(MOVBQZX s:(SET(EQ|NE|L|G|LE|GE|A|B|AE|BE) flags)) x)) && t.Block == s.Block => (CMOVL(NE|EQ|GE|LE|GT|LT|LS|CC|CS|HI) yes no flags)
1915 (CMOVLEQ yes no t:(TESTW x:(MOVBQZX s:(SET(EQ|NE|L|G|LE|GE|A|B|AE|BE) flags)) x)) && t.Block == s.Block => (CMOVL(NE|EQ|GE|LE|GT|LT|LS|CC|CS|HI) yes no flags)
1916 (CMOVLEQ yes no t:(TESTB s:(SET(EQ|NE|L|G|LE|GE|A|B|AE|BE) flags) s)) && t.Block == s.Block => (CMOVL(NE|EQ|GE|LE|GT|LT|LS|CC|CS|HI) yes no flags)
1917
1918 (CMOVWEQ yes no t:(TESTQ x:(MOVBQZX s:(SET(EQ|NE|L|G|LE|GE|A|B|AE|BE) flags)) x)) && t.Block == s.Block => (CMOVW(NE|EQ|GE|LE|GT|LT|LS|CC|CS|HI) yes no flags)
1919 (CMOVWEQ yes no t:(TESTL x:(MOVBQZX s:(SET(EQ|NE|L|G|LE|GE|A|B|AE|BE) flags)) x)) && t.Block == s.Block => (CMOVW(NE|EQ|GE|LE|GT|LT|LS|CC|CS|HI) yes no flags)
1920 (CMOVWEQ yes no t:(TESTW x:(MOVBQZX s:(SET(EQ|NE|L|G|LE|GE|A|B|AE|BE) flags)) x)) && t.Block == s.Block => (CMOVW(NE|EQ|GE|LE|GT|LT|LS|CC|CS|HI) yes no flags)
1921 (CMOVWEQ yes no t:(TESTB s:(SET(EQ|NE|L|G|LE|GE|A|B|AE|BE) flags) s)) && t.Block == s.Block => (CMOVW(NE|EQ|GE|LE|GT|LT|LS|CC|CS|HI) yes no flags)
1922
1923 (SETEQ t:(TESTQ x:(MOVBQZX s:(SET(EQ|NE|L|G|LE|GE|A|B|AE|BE) flags)) x)) && t.Block == s.Block => (SET(NE|EQ|GE|LE|G|L|BE|AE|B|A) flags)
1924 (SETEQ t:(TESTL x:(MOVBQZX s:(SET(EQ|NE|L|G|LE|GE|A|B|AE|BE) flags)) x)) && t.Block == s.Block => (SET(NE|EQ|GE|LE|G|L|BE|AE|B|A) flags)
1925 (SETEQ t:(TESTW x:(MOVBQZX s:(SET(EQ|NE|L|G|LE|GE|A|B|AE|BE) flags)) x)) && t.Block == s.Block => (SET(NE|EQ|GE|LE|G|L|BE|AE|B|A) flags)
1926 (SETEQ t:(TESTB s:(SET(EQ|NE|L|G|LE|GE|A|B|AE|BE) flags) s)) && t.Block == s.Block => (SET(NE|EQ|GE|LE|G|L|BE|AE|B|A) flags)
1927
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