intel.go

     1  // Copyright 2014 The Go Authors.  All rights reserved.
     2  // Use of this source code is governed by a BSD-style
     3  // license that can be found in the LICENSE file.
     4  
     5  package x86asm
     6  
     7  import (
     8  	"fmt"
     9  	"strings"
    10  )
    11  
    12  // IntelSyntax returns the Intel assembler syntax for the instruction, as defined by Intel's XED tool.
    13  func IntelSyntax(inst Inst, pc uint64, symname SymLookup) string {
    14  	if symname == nil {
    15  		symname = func(uint64) (string, uint64) { return "", 0 }
    16  	}
    17  
    18  	var iargs []Arg
    19  	for _, a := range inst.Args {
    20  		if a == nil {
    21  			break
    22  		}
    23  		iargs = append(iargs, a)
    24  	}
    25  
    26  	switch inst.Op {
    27  	case INSB, INSD, INSW, OUTSB, OUTSD, OUTSW, LOOPNE, JCXZ, JECXZ, JRCXZ, LOOP, LOOPE, MOV, XLATB:
    28  		if inst.Op == MOV && (inst.Opcode>>16)&0xFFFC != 0x0F20 {
    29  			break
    30  		}
    31  		for i, p := range inst.Prefix {
    32  			if p&0xFF == PrefixAddrSize {
    33  				inst.Prefix[i] &^= PrefixImplicit
    34  			}
    35  		}
    36  	}
    37  
    38  	switch inst.Op {
    39  	case MOV:
    40  		dst, _ := inst.Args[0].(Reg)
    41  		src, _ := inst.Args[1].(Reg)
    42  		if ES <= dst && dst <= GS && EAX <= src && src <= R15L {
    43  			src -= EAX - AX
    44  			iargs[1] = src
    45  		}
    46  		if ES <= dst && dst <= GS && RAX <= src && src <= R15 {
    47  			src -= RAX - AX
    48  			iargs[1] = src
    49  		}
    50  
    51  		if inst.Opcode>>24&^3 == 0xA0 {
    52  			for i, p := range inst.Prefix {
    53  				if p&0xFF == PrefixAddrSize {
    54  					inst.Prefix[i] |= PrefixImplicit
    55  				}
    56  			}
    57  		}
    58  	}
    59  
    60  	switch inst.Op {
    61  	case AAM, AAD:
    62  		if imm, ok := iargs[0].(Imm); ok {
    63  			if inst.DataSize == 32 {
    64  				iargs[0] = Imm(uint32(int8(imm)))
    65  			} else if inst.DataSize == 16 {
    66  				iargs[0] = Imm(uint16(int8(imm)))
    67  			}
    68  		}
    69  
    70  	case PUSH:
    71  		if imm, ok := iargs[0].(Imm); ok {
    72  			iargs[0] = Imm(uint32(imm))
    73  		}
    74  	}
    75  
    76  	for _, p := range inst.Prefix {
    77  		if p&PrefixImplicit != 0 {
    78  			for j, pj := range inst.Prefix {
    79  				if pj&0xFF == p&0xFF {
    80  					inst.Prefix[j] |= PrefixImplicit
    81  				}
    82  			}
    83  		}
    84  	}
    85  
    86  	if inst.Op != 0 {
    87  		for i, p := range inst.Prefix {
    88  			switch p &^ PrefixIgnored {
    89  			case PrefixData16, PrefixData32, PrefixCS, PrefixDS, PrefixES, PrefixSS:
    90  				inst.Prefix[i] |= PrefixImplicit
    91  			}
    92  			if p.IsREX() {
    93  				inst.Prefix[i] |= PrefixImplicit
    94  			}
    95  			if p.IsVEX() {
    96  				if p == PrefixVEX3Bytes {
    97  					inst.Prefix[i+2] |= PrefixImplicit
    98  				}
    99  				inst.Prefix[i] |= PrefixImplicit
   100  				inst.Prefix[i+1] |= PrefixImplicit
   101  			}
   102  			if p.IsEVEX() {
   103  				inst.Prefix[i] |= PrefixImplicit
   104  				inst.Prefix[i+1] |= PrefixImplicit
   105  				inst.Prefix[i+2] |= PrefixImplicit
   106  				inst.Prefix[i+3] |= PrefixImplicit
   107  			}
   108  		}
   109  	}
   110  
   111  	if isLoop[inst.Op] || inst.Op == JCXZ || inst.Op == JECXZ || inst.Op == JRCXZ {
   112  		for i, p := range inst.Prefix {
   113  			if p == PrefixPT || p == PrefixPN {
   114  				inst.Prefix[i] |= PrefixImplicit
   115  			}
   116  		}
   117  	}
   118  
   119  	switch inst.Op {
   120  	case AAA, AAS, CBW, CDQE, CLC, CLD, CLI, CLTS, CMC, CPUID, CQO, CWD, DAA, DAS,
   121  		FDECSTP, FINCSTP, FNCLEX, FNINIT, FNOP, FWAIT, HLT,
   122  		ICEBP, INSB, INSD, INSW, INT, INTO, INVD, IRET, IRETQ,
   123  		LAHF, LEAVE, LRET, MONITOR, MWAIT, NOP, OUTSB, OUTSD, OUTSW,
   124  		PAUSE, POPA, POPF, POPFQ, PUSHA, PUSHF, PUSHFQ,
   125  		RDMSR, RDPMC, RDTSC, RDTSCP, RET, RSM,
   126  		SAHF, STC, STD, STI, SYSENTER, SYSEXIT, SYSRET,
   127  		UD2, WBINVD, WRMSR, XEND, XLATB, XTEST:
   128  
   129  		if inst.Op == NOP && inst.Opcode>>24 != 0x90 {
   130  			break
   131  		}
   132  		if inst.Op == RET && inst.Opcode>>24 != 0xC3 {
   133  			break
   134  		}
   135  		if inst.Op == INT && inst.Opcode>>24 != 0xCC {
   136  			break
   137  		}
   138  		if inst.Op == LRET && inst.Opcode>>24 != 0xcb {
   139  			break
   140  		}
   141  		for i, p := range inst.Prefix {
   142  			if p&0xFF == PrefixDataSize {
   143  				inst.Prefix[i] &^= PrefixImplicit | PrefixIgnored
   144  			}
   145  		}
   146  
   147  	case 0:
   148  		// ok
   149  	}
   150  
   151  	switch inst.Op {
   152  	case INSB, INSD, INSW, OUTSB, OUTSD, OUTSW, MONITOR, MWAIT, XLATB:
   153  		iargs = nil
   154  
   155  	case STOSB, STOSW, STOSD, STOSQ:
   156  		iargs = iargs[:1]
   157  
   158  	case LODSB, LODSW, LODSD, LODSQ, SCASB, SCASW, SCASD, SCASQ:
   159  		iargs = iargs[1:]
   160  	}
   161  
   162  	const (
   163  		haveData16 = 1 << iota
   164  		haveData32
   165  		haveAddr16
   166  		haveAddr32
   167  		haveXacquire
   168  		haveXrelease
   169  		haveLock
   170  		haveHintTaken
   171  		haveHintNotTaken
   172  		haveBnd
   173  	)
   174  	var prefixBits uint32
   175  	prefix := ""
   176  	for _, p := range inst.Prefix {
   177  		if p == 0 {
   178  			break
   179  		}
   180  		if p&0xFF == 0xF3 {
   181  			prefixBits &^= haveBnd
   182  		}
   183  		if p&(PrefixImplicit|PrefixIgnored) != 0 {
   184  			continue
   185  		}
   186  		switch p {
   187  		default:
   188  			prefix += strings.ToLower(p.String()) + " "
   189  		case PrefixCS, PrefixDS, PrefixES, PrefixFS, PrefixGS, PrefixSS:
   190  			if inst.Op == 0 {
   191  				prefix += strings.ToLower(p.String()) + " "
   192  			}
   193  		case PrefixREPN:
   194  			prefix += "repne "
   195  		case PrefixLOCK:
   196  			prefixBits |= haveLock
   197  		case PrefixData16, PrefixDataSize:
   198  			prefixBits |= haveData16
   199  		case PrefixData32:
   200  			prefixBits |= haveData32
   201  		case PrefixAddrSize, PrefixAddr16:
   202  			prefixBits |= haveAddr16
   203  		case PrefixAddr32:
   204  			prefixBits |= haveAddr32
   205  		case PrefixXACQUIRE:
   206  			prefixBits |= haveXacquire
   207  		case PrefixXRELEASE:
   208  			prefixBits |= haveXrelease
   209  		case PrefixPT:
   210  			prefixBits |= haveHintTaken
   211  		case PrefixPN:
   212  			prefixBits |= haveHintNotTaken
   213  		case PrefixBND:
   214  			prefixBits |= haveBnd
   215  		}
   216  	}
   217  	switch inst.Op {
   218  	case JMP:
   219  		if inst.Opcode>>24 == 0xEB {
   220  			prefixBits &^= haveBnd
   221  		}
   222  	case RET, LRET:
   223  		prefixBits &^= haveData16 | haveData32
   224  	}
   225  
   226  	if prefixBits&haveXacquire != 0 {
   227  		prefix += "xacquire "
   228  	}
   229  	if prefixBits&haveXrelease != 0 {
   230  		prefix += "xrelease "
   231  	}
   232  	if prefixBits&haveLock != 0 {
   233  		prefix += "lock "
   234  	}
   235  	if prefixBits&haveBnd != 0 {
   236  		prefix += "bnd "
   237  	}
   238  	if prefixBits&haveHintTaken != 0 {
   239  		prefix += "hint-taken "
   240  	}
   241  	if prefixBits&haveHintNotTaken != 0 {
   242  		prefix += "hint-not-taken "
   243  	}
   244  	if prefixBits&haveAddr16 != 0 {
   245  		prefix += "addr16 "
   246  	}
   247  	if prefixBits&haveAddr32 != 0 {
   248  		prefix += "addr32 "
   249  	}
   250  	if prefixBits&haveData16 != 0 {
   251  		prefix += "data16 "
   252  	}
   253  	if prefixBits&haveData32 != 0 {
   254  		prefix += "data32 "
   255  	}
   256  
   257  	if inst.Op == 0 {
   258  		if prefix == "" {
   259  			return "<no instruction>"
   260  		}
   261  		return prefix[:len(prefix)-1]
   262  	}
   263  
   264  	var args []string
   265  	for i, a := range iargs {
   266  		if a == nil {
   267  			break
   268  		}
   269  		argStr := intelArg(&inst, pc, symname, a)
   270  		if i == 1 {
   271  			r, ok := a.(Reg)
   272  			if ok && K1 <= r && r <= K7 {
   273  				if !strings.HasPrefix(inst.Op.String(), "K") {
   274  					isPF := strings.HasPrefix(inst.Op.String(), "VGATHERPF") || strings.HasPrefix(inst.Op.String(), "VSCATTERPF")
   275  					if isPF {
   276  						args = append([]string{fmt.Sprintf("{%s}", argStr)}, args...)
   277  					} else if len(args) > 0 {
   278  						args[len(args)-1] += fmt.Sprintf(" {%s}", argStr)
   279  						if inst.Zeroing {
   280  							args[len(args)-1] += " {z}"
   281  						}
   282  					}
   283  					continue
   284  				}
   285  			} else if ok && r == K0 {
   286  				if !strings.HasPrefix(inst.Op.String(), "K") {
   287  					isPF := strings.HasPrefix(inst.Op.String(), "VGATHERPF") || strings.HasPrefix(inst.Op.String(), "VSCATTERPF")
   288  					if isPF {
   289  						args = append([]string{fmt.Sprintf("{%s}", argStr)}, args...)
   290  					} else if inst.Zeroing && len(args) > 0 {
   291  						args[len(args)-1] += " {z}"
   292  					}
   293  					continue
   294  				}
   295  			}
   296  		}
   297  		if _, ok := a.(Mem); ok && inst.Broadcast && len(args) > 0 {
   298  			// Find vector size from first argument (destination)
   299  			if dstReg, ok := iargs[0].(Reg); ok {
   300  				var vBytes int
   301  				if X0 <= dstReg && dstReg <= X31 {
   302  					vBytes = 16
   303  				} else if Y0 <= dstReg && dstReg <= Y31 {
   304  					vBytes = 32
   305  				} else if Z0 <= dstReg && dstReg <= Z31 {
   306  					vBytes = 64
   307  				}
   308  				if vBytes > 0 && inst.MemBytes > 0 {
   309  					argStr += fmt.Sprintf("{1to%d}", vBytes/inst.MemBytes)
   310  				}
   311  			}
   312  		}
   313  		args = append(args, argStr)
   314  	}
   315  
   316  	var op string
   317  	switch inst.Op {
   318  	case NOP:
   319  		if inst.Opcode>>24 == 0x0F {
   320  			if inst.DataSize == 16 {
   321  				args = append(args, "ax")
   322  			} else {
   323  				args = append(args, "eax")
   324  			}
   325  		}
   326  
   327  	case BLENDVPD, BLENDVPS, PBLENDVB:
   328  		args = args[:2]
   329  
   330  	case INT:
   331  		if inst.Opcode>>24 == 0xCC {
   332  			args = nil
   333  			op = "int3"
   334  		}
   335  
   336  	case LCALL, LJMP:
   337  		if len(args) == 2 {
   338  			args[0], args[1] = args[1], args[0]
   339  		}
   340  
   341  	case VCMPPD, VCMPPS, VCMPSD, VCMPSS, VCMPPH, VCMPSH, VCMPBF16:
   342  		for i := len(inst.Args) - 1; i >= 0; i-- {
   343  			if imm, ok := inst.Args[i].(Imm); ok {
   344  				if 0 <= imm && imm < 8 {
   345  					args = args[:len(args)-1]
   346  					baseOp := intelOp[inst.Op]
   347  					if baseOp == "" {
   348  						baseOp = strings.ToLower(inst.Op.String())
   349  					}
   350  					op = "v" + cmppsOps[imm] + baseOp[4:]
   351  				}
   352  				break
   353  			}
   354  			if inst.Args[i] != nil {
   355  				break
   356  			}
   357  		}
   358  
   359  	case FCHS, FABS, FTST, FLDPI, FLDL2E, FLDLG2, F2XM1, FXAM, FLD1, FLDL2T, FSQRT, FRNDINT, FCOS, FSIN:
   360  		if len(args) == 0 {
   361  			args = append(args, "st0")
   362  		}
   363  
   364  	case FPTAN, FSINCOS, FUCOMPP, FCOMPP, FYL2X, FPATAN, FXTRACT, FPREM1, FPREM, FYL2XP1, FSCALE:
   365  		if len(args) == 0 {
   366  			args = []string{"st0", "st1"}
   367  		}
   368  
   369  	case FST, FSTP, FISTTP, FIST, FISTP, FBSTP:
   370  		if len(args) == 1 {
   371  			args = append(args, "st0")
   372  		}
   373  
   374  	case FLD, FXCH, FCOM, FCOMP, FIADD, FIMUL, FICOM, FICOMP, FISUBR, FIDIV, FUCOM, FUCOMP, FILD, FBLD, FADD, FMUL, FSUB, FSUBR, FISUB, FDIV, FDIVR, FIDIVR:
   375  		if len(args) == 1 {
   376  			args = []string{"st0", args[0]}
   377  		}
   378  
   379  	case MASKMOVDQU, MASKMOVQ, XLATB, OUTSB, OUTSW, OUTSD:
   380  	FixSegment:
   381  		for i := len(inst.Prefix) - 1; i >= 0; i-- {
   382  			p := inst.Prefix[i] & 0xFF
   383  			switch p {
   384  			case PrefixCS, PrefixES, PrefixFS, PrefixGS, PrefixSS:
   385  				if inst.Mode != 64 || p == PrefixFS || p == PrefixGS {
   386  					args = append(args, strings.ToLower((inst.Prefix[i] & 0xFF).String()))
   387  					break FixSegment
   388  				}
   389  			case PrefixDS:
   390  				if inst.Mode != 64 {
   391  					break FixSegment
   392  				}
   393  			}
   394  		}
   395  	}
   396  
   397  	if inst.SAE {
   398  		if hasRC(inst.Op) {
   399  			switch inst.Rounding {
   400  			case 0:
   401  				args = append(args, "{rn-sae}")
   402  			case 1:
   403  				args = append(args, "{rd-sae}")
   404  			case 2:
   405  				args = append(args, "{ru-sae}")
   406  			case 3:
   407  				args = append(args, "{rz-sae}")
   408  			}
   409  		} else {
   410  			args = append(args, "{sae}")
   411  		}
   412  	}
   413  
   414  	if op == "" {
   415  		op = intelOp[inst.Op]
   416  	}
   417  	if op == "" {
   418  		op = strings.ToLower(inst.Op.String())
   419  	}
   420  	if args != nil {
   421  		op += " " + strings.Join(args, ", ")
   422  	}
   423  	return prefix + op
   424  }
   425  
   426  func intelArg(inst *Inst, pc uint64, symname SymLookup, arg Arg) string {
   427  	switch a := arg.(type) {
   428  	case Imm:
   429  		if (inst.Op == MOV || inst.Op == PUSH) && inst.DataSize == 32 { // See comment in plan9x.go.
   430  			if s, base := symname(uint64(a)); s != "" {
   431  				suffix := ""
   432  				if uint64(a) != base {
   433  					suffix = fmt.Sprintf("%+d", uint64(a)-base)
   434  				}
   435  				return fmt.Sprintf("$%s%s", s, suffix)
   436  			}
   437  		}
   438  		if inst.Mode == 32 {
   439  			return fmt.Sprintf("%#x", uint32(a))
   440  		}
   441  		if Imm(int32(a)) == a {
   442  			return fmt.Sprintf("%#x", int64(a))
   443  		}
   444  		return fmt.Sprintf("%#x", uint64(a))
   445  	case Mem:
   446  		if a.Base == EIP {
   447  			a.Base = RIP
   448  		}
   449  		prefix := ""
   450  		switch inst.MemBytes {
   451  		case 1:
   452  			prefix = "byte "
   453  		case 2:
   454  			prefix = "word "
   455  		case 4:
   456  			prefix = "dword "
   457  		case 8:
   458  			prefix = "qword "
   459  		case 16:
   460  			prefix = "xmmword "
   461  		case 32:
   462  			prefix = "ymmword "
   463  		case 64:
   464  			prefix = "zmmword "
   465  		}
   466  		if isVSIB(inst.Op) {
   467  			switch inst.Op {
   468  			case VPGATHERDD, VPSCATTERDD, VPGATHERQD, VPSCATTERQD, VGATHERDPS, VSCATTERDPS, VGATHERQPS, VSCATTERQPS, VGATHERPF0DPS, VGATHERPF1DPS, VSCATTERPF0DPS, VSCATTERPF1DPS, VGATHERPF0QPS, VGATHERPF1QPS, VSCATTERPF0QPS, VSCATTERPF1QPS:
   469  				prefix = "dword "
   470  			case VPGATHERDQ, VPSCATTERDQ, VPGATHERQQ, VPSCATTERQQ, VGATHERDPD, VSCATTERDPD, VGATHERQPD, VSCATTERQPD, VGATHERPF0DPD, VGATHERPF1DPD, VSCATTERPF0DPD, VSCATTERPF1DPD, VGATHERPF0QPD, VGATHERPF1QPD, VSCATTERPF0QPD, VSCATTERPF1QPD:
   471  				prefix = "qword "
   472  			}
   473  		}
   474  		switch inst.Op {
   475  		case INVLPG:
   476  			prefix = "byte "
   477  		case STOSB, MOVSB, CMPSB, LODSB, SCASB:
   478  			prefix = "byte "
   479  		case STOSW, MOVSW, CMPSW, LODSW, SCASW:
   480  			prefix = "word "
   481  		case STOSD, MOVSD, CMPSD, LODSD, SCASD:
   482  			prefix = "dword "
   483  		case STOSQ, MOVSQ, CMPSQ, LODSQ, SCASQ:
   484  			prefix = "qword "
   485  		case LAR:
   486  			prefix = "word "
   487  		case BOUND:
   488  			if inst.Mode == 32 {
   489  				prefix = "qword "
   490  			} else {
   491  				prefix = "dword "
   492  			}
   493  		case PREFETCHW, PREFETCHNTA, PREFETCHT0, PREFETCHT1, PREFETCHT2, CLFLUSH:
   494  			prefix = "zmmword "
   495  		}
   496  		switch inst.Op {
   497  		case MOVSB, MOVSW, MOVSD, MOVSQ, CMPSB, CMPSW, CMPSD, CMPSQ, STOSB, STOSW, STOSD, STOSQ, SCASB, SCASW, SCASD, SCASQ, LODSB, LODSW, LODSD, LODSQ:
   498  			switch a.Base {
   499  			case DI, EDI, RDI:
   500  				if a.Segment == ES {
   501  					a.Segment = 0
   502  				}
   503  			case SI, ESI, RSI:
   504  				if a.Segment == DS {
   505  					a.Segment = 0
   506  				}
   507  			}
   508  		case LEA:
   509  			a.Segment = 0
   510  		default:
   511  			switch a.Base {
   512  			case SP, ESP, RSP, BP, EBP, RBP:
   513  				if a.Segment == SS {
   514  					a.Segment = 0
   515  				}
   516  			default:
   517  				if a.Segment == DS {
   518  					a.Segment = 0
   519  				}
   520  			}
   521  		}
   522  
   523  		if inst.Mode == 64 && a.Segment != FS && a.Segment != GS {
   524  			a.Segment = 0
   525  		}
   526  
   527  		prefix += "ptr "
   528  		if s, disp := memArgToSymbol(a, pc, inst.Len, symname); s != "" {
   529  			suffix := ""
   530  			if disp != 0 {
   531  				suffix = fmt.Sprintf("%+d", disp)
   532  			}
   533  			return prefix + fmt.Sprintf("[%s%s]", s, suffix)
   534  		}
   535  		if a.Segment != 0 {
   536  			prefix += strings.ToLower(a.Segment.String()) + ":"
   537  		}
   538  		prefix += "["
   539  		if a.Base != 0 {
   540  			prefix += intelArg(inst, pc, symname, a.Base)
   541  		}
   542  		if a.Scale != 0 && a.Index != 0 {
   543  			if a.Base != 0 {
   544  				prefix += "+"
   545  			}
   546  			if a.Scale == 1 {
   547  				if inst.AddrSize == 16 || inst.Op.String() == "VMOVNTDQA" {
   548  					prefix += fmt.Sprintf("%s*1", intelArg(inst, pc, symname, a.Index))
   549  				} else if a.Base == 0 && ((X0 <= a.Index && a.Index <= Z31) || (M0 <= a.Index && a.Index <= M7)) {
   550  					prefix += fmt.Sprintf("1*%s", intelArg(inst, pc, symname, a.Index))
   551  				} else {
   552  					prefix += fmt.Sprintf("%s", intelArg(inst, pc, symname, a.Index))
   553  				}
   554  			} else {
   555  				prefix += fmt.Sprintf("%d*%s", a.Scale, intelArg(inst, pc, symname, a.Index))
   556  			}
   557  		}
   558  		if a.Disp != 0 {
   559  			if prefix[len(prefix)-1] == '[' && (a.Disp >= 0 || int64(int32(a.Disp)) != a.Disp) {
   560  				prefix += fmt.Sprintf("%#x", uint64(a.Disp))
   561  			} else {
   562  				prefix += fmt.Sprintf("%+#x", a.Disp)
   563  			}
   564  		}
   565  		prefix += "]"
   566  		return prefix
   567  	case Rel:
   568  		if pc == 0 {
   569  			return fmt.Sprintf(".%+#x", int64(a))
   570  		} else {
   571  			addr := pc + uint64(inst.Len) + uint64(a)
   572  			if s, base := symname(addr); s != "" && addr == base {
   573  				return fmt.Sprintf("%s", s)
   574  			} else {
   575  				addr := pc + uint64(inst.Len) + uint64(a)
   576  				return fmt.Sprintf("%#x", addr)
   577  			}
   578  		}
   579  	case Reg:
   580  		if int(a) < len(intelReg) && intelReg[a] != "" {
   581  			return intelReg[a]
   582  		}
   583  	}
   584  	return strings.ToLower(arg.String())
   585  }
   586  
   587  var intelOp = map[Op]string{
   588  	JAE:       "jnb",
   589  	JA:        "jnbe",
   590  	JGE:       "jnl",
   591  	JNE:       "jnz",
   592  	JG:        "jnle",
   593  	JE:        "jz",
   594  	SETAE:     "setnb",
   595  	SETA:      "setnbe",
   596  	SETGE:     "setnl",
   597  	SETNE:     "setnz",
   598  	SETG:      "setnle",
   599  	SETE:      "setz",
   600  	CMOVAE:    "cmovnb",
   601  	CMOVA:     "cmovnbe",
   602  	CMOVGE:    "cmovnl",
   603  	CMOVNE:    "cmovnz",
   604  	CMOVG:     "cmovnle",
   605  	CMOVE:     "cmovz",
   606  	LCALL:     "call far",
   607  	LJMP:      "jmp far",
   608  	LRET:      "ret far",
   609  	ICEBP:     "int1",
   610  	MOVSD_XMM: "movsd",
   611  	XLATB:     "xlat",
   612  }
   613  
   614  var intelReg = [...]string{
   615  	F0:  "st0",
   616  	F1:  "st1",
   617  	F2:  "st2",
   618  	F3:  "st3",
   619  	F4:  "st4",
   620  	F5:  "st5",
   621  	F6:  "st6",
   622  	F7:  "st7",
   623  	M0:  "mmx0",
   624  	M1:  "mmx1",
   625  	M2:  "mmx2",
   626  	M3:  "mmx3",
   627  	M4:  "mmx4",
   628  	M5:  "mmx5",
   629  	M6:  "mmx6",
   630  	M7:  "mmx7",
   631  	X0:  "xmm0",
   632  	X1:  "xmm1",
   633  	X2:  "xmm2",
   634  	X3:  "xmm3",
   635  	X4:  "xmm4",
   636  	X5:  "xmm5",
   637  	X6:  "xmm6",
   638  	X7:  "xmm7",
   639  	X8:  "xmm8",
   640  	X9:  "xmm9",
   641  	X10: "xmm10",
   642  	X11: "xmm11",
   643  	X12: "xmm12",
   644  	X13: "xmm13",
   645  	X14: "xmm14",
   646  	X15: "xmm15",
   647  	X16: "xmm16",
   648  	X17: "xmm17",
   649  	X18: "xmm18",
   650  	X19: "xmm19",
   651  	X20: "xmm20",
   652  	X21: "xmm21",
   653  	X22: "xmm22",
   654  	X23: "xmm23",
   655  	X24: "xmm24",
   656  	X25: "xmm25",
   657  	X26: "xmm26",
   658  	X27: "xmm27",
   659  	X28: "xmm28",
   660  	X29: "xmm29",
   661  	X30: "xmm30",
   662  	X31: "xmm31",
   663  	Y0:  "ymm0",
   664  	Y1:  "ymm1",
   665  	Y2:  "ymm2",
   666  	Y3:  "ymm3",
   667  	Y4:  "ymm4",
   668  	Y5:  "ymm5",
   669  	Y6:  "ymm6",
   670  	Y7:  "ymm7",
   671  	Y8:  "ymm8",
   672  	Y9:  "ymm9",
   673  	Y10: "ymm10",
   674  	Y11: "ymm11",
   675  	Y12: "ymm12",
   676  	Y13: "ymm13",
   677  	Y14: "ymm14",
   678  	Y15: "ymm15",
   679  	Y16: "ymm16",
   680  	Y17: "ymm17",
   681  	Y18: "ymm18",
   682  	Y19: "ymm19",
   683  	Y20: "ymm20",
   684  	Y21: "ymm21",
   685  	Y22: "ymm22",
   686  	Y23: "ymm23",
   687  	Y24: "ymm24",
   688  	Y25: "ymm25",
   689  	Y26: "ymm26",
   690  	Y27: "ymm27",
   691  	Y28: "ymm28",
   692  	Y29: "ymm29",
   693  	Y30: "ymm30",
   694  	Y31: "ymm31",
   695  	Z0:  "zmm0",
   696  	Z1:  "zmm1",
   697  	Z2:  "zmm2",
   698  	Z3:  "zmm3",
   699  	Z4:  "zmm4",
   700  	Z5:  "zmm5",
   701  	Z6:  "zmm6",
   702  	Z7:  "zmm7",
   703  	Z8:  "zmm8",
   704  	Z9:  "zmm9",
   705  	Z10: "zmm10",
   706  	Z11: "zmm11",
   707  	Z12: "zmm12",
   708  	Z13: "zmm13",
   709  	Z14: "zmm14",
   710  	Z15: "zmm15",
   711  	Z16: "zmm16",
   712  	Z17: "zmm17",
   713  	Z18: "zmm18",
   714  	Z19: "zmm19",
   715  	Z20: "zmm20",
   716  	Z21: "zmm21",
   717  	Z22: "zmm22",
   718  	Z23: "zmm23",
   719  	Z24: "zmm24",
   720  	Z25: "zmm25",
   721  	Z26: "zmm26",
   722  	Z27: "zmm27",
   723  	Z28: "zmm28",
   724  	Z29: "zmm29",
   725  	Z30: "zmm30",
   726  	Z31: "zmm31",
   727  	K0:  "k0",
   728  	K1:  "k1",
   729  	K2:  "k2",
   730  	K3:  "k3",
   731  	K4:  "k4",
   732  	K5:  "k5",
   733  	K6:  "k6",
   734  	K7:  "k7",
   735  
   736  	// TODO: Maybe the constants are named wrong.
   737  	SPB: "spl",
   738  	BPB: "bpl",
   739  	SIB: "sil",
   740  	DIB: "dil",
   741  
   742  	R8L:  "r8d",
   743  	R9L:  "r9d",
   744  	R10L: "r10d",
   745  	R11L: "r11d",
   746  	R12L: "r12d",
   747  	R13L: "r13d",
   748  	R14L: "r14d",
   749  	R15L: "r15d",
   750  }
   751
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